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S1D13706 Embedded Memory LCD Controller
Hardware Functional Specification
Document Number: X31B-A-001-09
Copyright (c) 1999, 2004 Epson Research and Development, Inc. All Rights Reserved. Information in this document is subject to change without notice. You may download and use this document, but only for your own use in evaluating Seiko Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws. EPSON is a registered trademark of Seiko Epson Corporation. All other Trademarks are the property of their respective owners
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S1D13706 X31B-A-001-09
Hardware Functional Specification Issue Date: 2004/02/09
Epson Research and Development Vancouver Design Center
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Table of Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.2 Overview Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Features . . . . . . . . . . 2.1 Integrated Frame Buffer 2.2 CPU Interface . . . . 2.3 Display Support . . . . 2.4 Display Modes . . . . 2.5 Display Features . . . 2.6 Clock Source . . . . . 2.7 Miscellaneous . . . . . . . . . . . . .. . . . . . . . .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . .. . . . . . . . .. .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . ... .. .. .. .. .. .. .. . . . . . . . . . . . . . . . . . . . . . . . . 12 12 12 12 13 13 13 13
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3 4
Typical System Implementation Diagrams . . . . . . . . . . . . . . . . . . . . . . 14 Pins . . . . . . . . . . . . . . . . . 4.1 Pinout Diagram - TQFP15 - 100pin 4.2 Pinout Diagram - Die Form . . . 4.3 Pin Descriptions . . . . . . . 4.3.1 Host Interface . . . . . . . . 4.3.2 LCD Interface . . . . . . . . 4.3.3 Clock Input . . . . . . . . . 4.3.4 Miscellaneous . . . . . . . . 4.3.5 Power And Ground . . . . . 4.4 Summary of Configuration Options 4.5 Host Bus Interface Pin Mapping . 4.6 LCD Interface Pin Mapping . . . . . . . . . . . . . . . ... .. .. .. ... ... ... ... ... .. .. .. .... .... .... .... ..... ..... ..... ..... ..... .... .... .... ... .. .. .. ... ... ... ... ... .. .. .. . . . . . . . . . . . . ...... ..... ..... ..... ....... ....... ....... ....... ....... ..... ..... ..... . . . . . . . . . . . . ....... ...... ...... ...... ........ ........ ........ ........ ........ ...... ...... ...... 18 18 19 21 21 25 27 27 27 28 29 30
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D.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 A.C. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 Clock Timing . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.2 Internal Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.2 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . 6.2.1 Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . 6.2.2 Generic #2 Interface Timing (e.g. ISA) . . . . . . . . . . . . . . . 6.2.3 Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . 6.2.4 Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . 6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000) . . . . . . 6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030) . . . . . . . . . . . . . . . . . ... .. ... ... .. ... ... ... ... ... ... .... .... ..... ..... .... ..... ..... ..... ..... ..... ..... 32 32 32 34 35 35 37 39 41 43 45
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6.2.7 Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 47 6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328) 49 6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328) 51 6.3 LCD Power Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . .54 6.3.1 Passive/TFT Power-On Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 6.3.2 Passive/TFT Power-Off Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 6.4 Display Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 6.4.1 Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6.4.2 Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 60 6.4.3 Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . 62 6.4.4 Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6.4.5 Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . 66 6.4.6 Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . 68 6.4.7 Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.4.8 Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.4.9 9/12/18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 6.4.10 160x160 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx) . . . . . . . 76 6.4.11 320x240 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ039Q2DS01) . . . . . . . . 80 6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR) . . . . . . . . . . . . . . . . 82 6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR) . . . . . . . . . . . . . . . . 86 7 Clocks . . . . . . . . . . . 7.1 Clock Descriptions . . 7.1.1 BCLK . . . . . . 7.1.2 MCLK . . . . . . 7.1.3 PCLK . . . . . . 7.1.4 PWMCLK . . . . 7.2 Clock Selection . . . 7.3 Clocks versus Functions . . . . . . . . ...... ..... ....... ....... ....... ....... ..... ..... . . . . . . . . ... .. ... ... ... ... .. .. .... .... ..... ..... ..... ..... .... .... .... .... .... .... ..... ..... ..... ..... ..... ..... ..... ... .. ... ... ... ... .. .. ... .. .. .. ... ... ... ... ... ... ... . . . . . . . . . . . . . . . . . . . ...... ..... ....... ....... ....... ....... ..... ..... ...... ..... ..... ..... ....... ....... ....... ....... ....... ....... ....... . . . . . . . . . . . . . . . . . . . . . . . . .90 . . . . .90 . . . . . . 90 . . . . . . 90 . . . . . . 91 . . . . . . 92 . . . . .93 . . . . .94 ... .. .. .. ... ... ... ... ... ... ... . . .95 . . .95 . . .95 . . .96 . . . 96 . . . 97 . . . 99 . . .101 . . .109 . . .115 . . .120
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Registers . . . . . . . . . . . . . . . . . . . . 8.1 Register Mapping . . . . . . . . . . . 8.2 Register Set . . . . . . . . . . . . . . 8.3 Register Descriptions . . . . . . . . . . 8.3.1 Read-Only Configuration Registers . . . 8.3.2 Clock Configuration Registers . . . . . 8.3.3 Look-Up Table Registers . . . . . . . . 8.3.4 Panel Configuration Registers . . . . . . 8.3.5 Display Mode Registers . . . . . . . . . 8.3.6 Picture-in-Picture Plus (PIP+) Registers 8.3.7 Miscellaneous Registers . . . . . . . . .
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8.3.8 8.3.9 9
General IO Pins Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers 126 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Frame Rate Calculation
10 Display Data Formats
11 Look-Up Table Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.1 Monochrome Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 11.2 Color Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 12 SwivelViewTM . . . . . . . . . . . . 12.1 Concept . . . . . . . . . . . 12.2 90 SwivelViewTM . . . . . . 12.2.1 Register Programming . . . 12.3 180 SwivelViewTM . . . . . . 12.3.1 Register Programming . . . 12.4 270 SwivelViewTM . . . . . . 12.4.1 Register Programming . . . 13 Picture-in-Picture Plus (PIP+) 13.1 Concept . . . . . . . . 13.2 With SwivelView Enabled 13.2.1 SwivelView 90 . . . 13.2.2 SwivelView 180 . . 13.2.3 SwivelView 270 . . ... ... ... .... .... .... . . . . . . . . . . . . . . . . . . ... .. .. ... .. ... .. ... ... .. .. ... ... ... .... .... .... ..... .... ..... .... ..... .... .... .... ..... ..... ..... ... .. .. ... .. ... .. ... ... .. .. ... ... ... ... .. ... ... . . . . . . . . . . . . . . . . . . ...... ..... ..... ....... ..... ....... ..... ....... ...... ..... ..... ....... ....... ....... ...... ..... ....... ....... . . . . . . . . . . . . . . . . . . ... .. .. ... .. ... .. ... . . . . 138 . . . . 138 . . . . 138 . . . . . 139 . . . . 140 . . . . . 140 . . . . 141 . . . . . 142
. . . . . . . 143 . . . . . . 143 . . . . . . 144 . . . . . . . . 144 . . . . . . . . 144 . . . . . . . . 145 . . . . . . . 146 . . . . . . 146 . . . . . . . . 147 . . . . . . . . 148
14 Big-Endian Bus Interface . . . . . 14.1 Byte Swapping Bus Data . . . . 14.1.1 16 Bpp Color Depth . . . . . 14.1.2 1/2/4/8 Bpp Color Depth . .
....... ...... ........ ........
15 Power Save Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 16 Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 17 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 18 Sales and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
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List of Tables
Table 4-1: Pinout Assignments - Die Form (S1D13706D00A) . . . . . . . . . . Table 4-2: Host Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . Table 4-3: LCD Interface Pin Descriptions . . . . . . . . . . . . . . . . . . . . Table 4-4: Clock Input Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . Table 4-5: Miscellaneous Pin Descriptions . . . . . . . . . . . . . . . . . . . . Table 4-6: Power And Ground Pin Descriptions . . . . . . . . . . . . . . . . . Table 4-7: Summary of Power-On/Reset Options . . . . . . . . . . . . . . . . . Table 4-8: Host Bus Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . Table 4-9: LCD Interface Pin Mapping . . . . . . . . . . . . . . . . . . . . . . Table 5-1: Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . Table 5-2: Recommended Operating Conditions . . . . . . . . . . . . . . . . . Table 5-3: Electrical Characteristics for VDD = 3.3V typical . . . . . . . . . . . Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1 Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1 Table 6-3: Clock Input Requirements for CLKI2 . . . . . . . . . . . . . . . . . Table 6-4: Internal Clock Requirements . . . . . . . . . . . . . . . . . . . . . . Table 6-5: Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . Table 6-6: Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . Table 6-7: Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . Table 6-8: Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . Table 6-9: Motorola MC68K #1 Interface Timing . . . . . . . . . . . . . . . . Table 6-10: Motorola MC68K #2 Interface Timing . . . . . . . . . . . . . . . . Table 6-11: Motorola REDCAP2 Interface Timing. . . . . . . . . . . . . . . . . Table 6-12: Motorola DragonBall Interface with DTACK Timing . . . . . . . . . Table 6-13: Motorola DragonBall Interface without DTACK Timing . . . . . . . Table 6-14: Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . Table 6-15: Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . . Table 6-16: Panel Timing Parameter Definition and Register Summary . . . . . . Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . Table 6-19: Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . Table 6-22: Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . Table 6-23: TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-24: 160x160 Sharp `Direct' HR-TFT Horizontal Timing . . . . . . . . . Table 6-25: 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 21 25 27 27 27 28 29 30 31 31 31 32 33 33 34 36 38 40 42 44 46 48 50 52 54 55 57 61 63 65 67 69 71 75 77 79
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Table 6-26: 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing Table 6-27: 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing . Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing . . . . . Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing . . Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing . . . . . . Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing . . . . . Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing . . Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing . . . . . . Table 7-1: BCLK Clock Selection . . . . . . . . . . . . . . . . . . . Table 7-2: MCLK Clock Selection. . . . . . . . . . . . . . . . . . . Table 7-3: PCLK Clock Selection . . . . . . . . . . . . . . . . . . . Table 7-4: Relationship between MCLK and PCLK. . . . . . . . . . Table 7-5: PWMCLK Clock Selection. . . . . . . . . . . . . . . . . Table 7-6: S1D13706 Internal Clock Requirements . . . . . . . . . . Table 8-1: S1D13706 Register Set . . . . . . . . . . . . . . . . . . . Table 8-2: MCLK Divide Selection . . . . . . . . . . . . . . . . . . Table 8-3: PCLK Divide Selection. . . . . . . . . . . . . . . . . . . Table 8-4: PCLK Source Selection. . . . . . . . . . . . . . . . . . . Table 8-5: Panel Data Width Selection . . . . . . . . . . . . . . . . Table 8-6: Active Panel Resolution Selection . . . . . . . . . . . . . Table 8-7: LCD Panel Type Selection . . . . . . . . . . . . . . . . . Table 8-8: Inverse Video Mode Select Options . . . . . . . . . . . . Table 8-9: LCD Bit-per-pixel Selection . . . . . . . . . . . . . . . . Table 8-10: SwivelViewTM Mode Select Options . . . . . . . . . . . Table 8-11: 32-bit Address Increments for Color Depth . . . . . . . . Table 8-12: 32-bit Address Increments for Color Depth . . . . . . . . Table 8-13: 32-bit Address Increments for Color Depth . . . . . . . . Table 8-14: 32-bit Address Increments for Color Depth . . . . . . . . Table 8-15: PWM Clock Control . . . . . . . . . . . . . . . . . . . . Table 8-16: CV Pulse Control . . . . . . . . . . . . . . . . . . . . . . Table 8-17: PWM Clock Divide Select Options . . . . . . . . . . . . Table 8-18: CV Pulse Divide Select Options . . . . . . . . . . . . . . Table 8-19: PWMOUT Duty Cycle Select Options . . . . . . . . . . . Table 15-1: Power Save Mode Function Summary . . . . . . . . . . .
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. 81 . 81 . 83 . 84 . 85 . 87 . 88 . 89 . 90 . 90 . 91 . 92 . 92 . 94 . 95 . 97 . 98 . 98 .102 .102 .102 .110 .111 .112 .116 .117 .118 .119 .126 .127 .128 .128 .129 .149
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List of Figures
Figure 3-1: Figure 3-2: Figure 3-3: Figure 3-4: Figure 3-5: Figure 3-6: Figure 3-7: Figure 3-8: Figure 4-1: Figure 4-2: Figure 6-1: Figure 6-2: Figure 6-3: Figure 6-4: Figure 6-5: Figure 6-6: Figure 6-7: Figure 6-8: Figure 6-9: Figure 6-10: Figure 6-11: Figure 6-12: Figure 6-13: Figure 6-14: Figure 6-15: Figure 6-16: Figure 6-17: Figure 6-18: Figure 6-19: Figure 6-20: Figure 6-21: Figure 6-22: Figure 6-23: Figure 6-24: Figure 6-25: Figure 6-26: Figure 6-27: Typical System Diagram (Generic #1 Bus) . . . . . . . . . . . . . . . . . . . . . . Typical System Diagram (Generic #2 Bus) . . . . . . . . . . . . . . . . . . . . . . Typical System Diagram (Hitachi SH-4 Bus) . . . . . . . . . . . . . . . . . . . . . Typical System Diagram (Hitachi SH-3 Bus) . . . . . . . . . . . . . . . . . . . . . Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000) . . . . . . . . . . . Typical System Diagram (MC68K #2, Motorola 32-Bit 68030) . . . . . . . . . . . . Typical System Diagram (Motorola REDCAP2 Bus) . . . . . . . . . . . . . . . . . Typical System Diagram (Motorola MC68EZ328/MC68VZ328 "DragonBall" Bus) . Pinout Diagram - TQFP15 - 100pin (S1D13706F00A) . . . . . . . . . . . . . . . . Pinout Diagram - Die Form (S1D13706D00A) . . . . . . . . . . . . . . . . . . . . Clock Input Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic #1 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic #2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hitachi SH-4 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hitachi SH-3 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Motorola MC68K #1 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . Motorola MC68K #2 Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . Motorola REDCAP2 Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . Motorola DragonBall Interface with DTACK Timing . . . . . . . . . . . . . . . . . Motorola DragonBall Interface without DTACK# Timing . . . . . . . . . . . . . . Passive/TFT Power-On Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . Passive/TFT Power-Off Sequence Timing . . . . . . . . . . . . . . . . . . . . . . . Panel Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic STN Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Monochrome 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . Single Monochrome 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . Single Monochrome 8-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . Single Monochrome 8-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . Single Color 4-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Color 4-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . Single Color 8-Bit Panel Timing (Format 1) . . . . . . . . . . . . . . . . . . . . . . Single Color 8-Bit Panel A.C. Timing (Format 1) . . . . . . . . . . . . . . . . . . . Single Color 8-Bit Panel Timing (Format 2) . . . . . . . . . . . . . . . . . . . . . . Single Color 8-Bit Panel A.C. Timing (Format 2) . . . . . . . . . . . . . . . . . . . Single Color 16-Bit Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Color 16-Bit Panel A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . Generic TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 . 14 . 15 . 15 . 16 . 16 . 17 . 17 . 18 . 19 . 32 . 35 . 37 . 39 . 41 . 43 . 45 . 47 . 49 . 51 . 54 . 55 . 56 . 58 . 60 . 61 . 62 . 63 . 64 . 65 . 66 . 67 . 68 . 69 . 70 . 71 . 72
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Figure 6-28: Figure 6-29: Figure 6-30: Figure 6-31: Figure 6-32: Figure 6-33: Figure 6-34: Figure 6-35: Figure 6-36: Figure 6-37: Figure 6-38: Figure 6-39: Figure 7-1: Figure 8-1: Figure 8-2: Figure 10-1: Figure 11-1: Figure 11-2: Figure 11-3: Figure 11-4: Figure 11-5: Figure 11-6: Figure 11-7: Figure 11-8: Figure 12-1: Figure 12-2: Figure 12-3: Figure 13-1: Figure 13-2: Figure 13-3: Figure 13-4: Figure 14-1: Figure 14-2: Figure 16-1:
18-Bit TFT Panel Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 TFT A.C. Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 160x160 Sharp `Direct' HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .76 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .78 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing . . . . . . . . . . . . . . . .80 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing. . . . . . . . . . . . . . . . . .81 160x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .82 160x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .84 160x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . .85 320x240 Epson D-TFD Panel Horizontal Timing . . . . . . . . . . . . . . . . . . . . .86 320x240 Epson D-TFD Panel GCP Horizontal Timing . . . . . . . . . . . . . . . . . .88 320x240 Epson D-TFD Panel Vertical Timing . . . . . . . . . . . . . . . . . . . . . . .89 Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Display Data Byte/Word Swap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 PWM Clock/CV Pulse Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4/8/16 Bit-Per-Pixel Display Data Memory Organization . . . . . . . . . . . . . . . . 131 1 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132 2 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 132 4 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133 8 Bit-per-pixel Monochrome Mode Data Output Path . . . . . . . . . . . . . . . . . . 133 1 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 134 2 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 135 4 Bit-Per-Pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 136 8 Bit-per-pixel Color Mode Data Output Path . . . . . . . . . . . . . . . . . . . . . . 137 Relationship Between The Screen Image and the Image Refreshed in 90x SwivelView. 138 Relationship Between The Screen Image and the Image Refreshed in 180x SwivelView.140 Relationship Between The Screen Image and the Image Refreshed in 270x SwivelView.141 Picture-in-Picture Plus with SwivelView disabled . . . . . . . . . . . . . . . . . . . . 143 Picture-in-Picture Plus with SwivelView 90 enabled . . . . . . . . . . . . . . . . . . 144 Picture-in-Picture Plus with SwivelView 180 enabled . . . . . . . . . . . . . . . . . 144 Picture-in-Picture Plus with SwivelView 270 enabled . . . . . . . . . . . . . . . . . 145 Byte-swapping for 16 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Byte-swapping for 1/2/4/8 Bpp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Mechanical Data 100pin TQFP15 (S1D13706F00A) . . . . . . . . . . . . . . . . . . 150
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1 Introduction
1.1 Scope
This is the Hardware Functional Specification for the S1D13706 Embedded Memory LCD Controller. Included in this document are timing diagrams, AC and DC characteristics, register descriptions, and power management descriptions. This document is intended for two audiences: Video Subsystem Designers and Software Developers. For additional documentation related to the S1D13706 see Section 17, "References" on page 151. This document is updated as appropriate. Please check the Epson Research and Development Website at www.erd.epson.com for the latest revision of this document before beginning any development. We appreciate your comments on our documentation. Please contact us via email at documentation@erd.epson.com.
1.2 Overview Description
The S1D13706 is a color/monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer. While supporting all other panel types, the S1D13706 is the only LCD controller to directly interface to both the Epson D-TFD and the Sharp HR-TFT family of products thus removing the requirement of an external Timing Control IC. This high level of integration provides a low cost, low power, single chip solution to meet the demands of embedded markets such as Mobile Communications devices and Palm-size PCs, where board size and battery life are major concerns. The S1D13706 utilizes a guaranteed low-latency CPU architecture providing support for microprocessors without READY/WAIT# handshaking signals. The 32-bit internal data path provides high performance bandwidth into display memory allowing for fast screen updates. Products requiring a rotated display image can take advantage of the SwivelView TM feature which provides hardware rotation of the display memory transparent to the software application. The S1D13706 also provides support for "Picture-in-Picture Plus" (a variable size Overlay window). The S1D13706 provides impressive support for Palm OS handhelds, however its impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications.
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2 Features
2.1 Integrated Frame Buffer
* Embedded 80K byte SRAM display buffer.
2.2 CPU Interface
* Direct support of the following interfaces: Generic MPU bus interface using WAIT# signal. Hitachi SH-3. Hitachi SH-4. Motorola M68K. Motorola MC68EZ328/MC68VZ328 DragonBall. Motorola "REDCAP2" - no WAIT# signal. * 8-bit processor support with "glue logic". * "Fixed" low-latency CPU access times. * Registers are memory-mapped - M/R# input selects between memory and register address space. * The complete 80K byte display buffer is directly and contiguously available through the 17-bit address bus. * Single level CPU write buffer.
2.3 Display Support
* Single-panel, single-drive passive displays. * 4/8-bit monochrome LCD interface. * 4/8/16-bit color LCD interface. * Active Matrix TFT interface. * 9/12/18-bit interface. * `Direct' support for 18-bit Epson D-TFD interface. * `Direct' support for 18-bit Sharp HR-TFT interface.
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2.4 Display Modes
* 1/2/4/8/16 bit-per-pixel (bpp) color depths. * Up to 64 gray shades using Frame Rate Modulation (FRM) and dithering on monochrome passive LCD panels. * Up to 64K colors on passive STN panels. * Up to 64K colors on active matrix LCD panels. * Example resolutions: 320x240 at a color depth of 8 bpp 160x160 at a color depth of 16 bpp 160x240 at a color depth of 16 bpp
2.5 Display Features
* SwivelViewTM: 90, 180, 270 counter-clockwise hardware rotation of display image. * "Picture-in-Picture Plus": displays a variable size window overlaid over background image. * Double Buffering/Multi-pages: provides smooth animation and instantaneous screen updates.
2.6 Clock Source
* Two clock inputs: CLKI and CLKI2. It is possible to use one clock input only. * Bus clock is derived from CLKI and can be internally divided by 2, 3, or 4. * Memory clock is derived from bus clock. It can be internally divided by 2, 3, or 4. * Pixel clock can be derived from CLKI, CLKI2, bus clock, or memory clock. It can be internally divided by 2, 3, 4, or 8.
2.7 Miscellaneous
* Hardware/Software Video Invert. * Software Power Save mode. * General Purpose Input/Output pins are available. * 100-pin TQFP15 package. * 104-pin CFLGA package. * Die form available.
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3 Typical System Implementation Diagrams
.
Oscillator
Generic #1 BUS
BS# A[27:17] Decoder M/R#
CLKI2
HIOVDD
FPDAT[15:0] FPFRAME
16-bit Single FPFRAME LCD Display
D[15:0] FPLINE FPSHIFT MOD Bias Power
CSn# A[16:1] D[15:0] WE0# WE1# RD0# RD1# WAIT# BUSCLK RESET# VSS
CS# AB[16:1] DB[15:0] WE0# WE1# RD# RD/WR# WAIT# CLKI RESET# AB0
FPLINE FPSHIFT DRDY
S1D13706
GPO
Figure 3-1: Typical System Diagram (Generic #1 Bus)
.
Oscillator
Generic #2 BUS
BS# RD/WR# A[27:17] CSn# A[16:0] D[15:0] WE# BHE# RD# Decoder M/R# CS# AB[16:0] DB[15:0] WE0# WE1# RD#
CLKI2
VDD
FPDAT[8:0] FPFRAME
D[8:0] FPFRAME
9-bit TFT Display
Bias Power
FPLINE FPSHIFT
FPLINE FPSHIFT DRDY
S1D13706
DRDY
GPO
WAIT#
WAIT#
BUSCLK RESET#
CLKI RESET#
Figure 3-2: Typical System Diagram (Generic #2 Bus)
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.
Oscillator
SH-4 BUS
CLKI2 A[25:17] Decoder M/R# FPDAT15 FPDAT12 CSn# A[16:1] D[15:0] WE0# WE1# BS# RD/WR# RD# CS# AB[16:1] DB[15:0] WE0# WE1# BS# RD/WR# RD# FPDAT[9:0] FPFRAME FPLINE FPSHIFT DRDY D11 D10 D[9:0] FPFRAME Bias Power FPLINE FPSHIFT DRDY
12-bit TFT Display
S1D13706
GPO
RDY# CKIO RESET# VSS
WAIT# CLKI RESET# AB0
Figure 3-3: Typical System Diagram (Hitachi SH-4 Bus)
.
Oscillator
SH-3 BUS
CLKI2 A[25:17] Decoder M/R#
FPDAT[17:0] CSn# A[16:1] D[15:0] WE0# WE1# BS# RD/WR# RD# CS# AB[16:1] DB[15:0] WE0# WE1# BS# RD/WR# RD# FPSHIFT DRDY FPFRAME
D[17:0] FPFRAME
18-bit TFT Display
Bias Power
FPLINE
FPLINE FPSHIFT DRDY
S1D13706
GPO
WAIT# CKIO RESET# VSS
WAIT# CLKI RESET# AB0
Figure 3-4: Typical System Diagram (Hitachi SH-3 Bus)
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.
Oscillator
MC68K #1 BUS
RD# WE0# A[23:17] FC0, FC1 Decoder M/R#
CLKI2
HIOVDD
FPDAT[17:0] FPFRAME FPLINE FPSHIFT
D[17:0] SPS LP CLK PS CLS REV SPL
18-bit HR-TFT Display
A[16:1] D[15:0] LDS# UDS# AS# R/W# DTACK#
AB[16:1] DB[15:0] AB0 WE1# BS# RD/WR# WAIT#
GPIO1 GPIO2 GPIO3
S1D13706
GPO
CLK RESET#
CLKI RESET#
Figure 3-5: Typical System Diagram (MC68K # 1, Motorola 16-Bit 68000)
.
Oscillator
MC68K #2 BUS
A[31:17] FC0, FC1 CLKI2 Decoder M/R# FPDAT[17:0] FPFRAME FPLINE FPSHIFT A[16:0] D[31:16] AB[16:0] DB[15:0] DRDY GPIO0 GPIO1 DS# AS# R/W# SIZ1 SIZ0 DSACK1# WE1# BS# RD/WR# RD# WE0# WAIT# GPO GPIO2 D[17:0] DY LP XSCL GCP XINH YSCL FRS RES DD_P1 YSCLD XSET (Bias Power) FR
Decoder
CS#
S1D13706
GPIO3 GPIO4 GPIO5 GPIO6
CLK RESET#
CLKI RESET#
Figure 3-6: Typical System Diagram (MC68K #2, Motorola 32-Bit 68030)
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Bias Power
Decoder
CS#
GPIO0
18-bit D-TFD Display
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.
Oscillator
BS# A[21:17] CSn A[16:1] D[15:0] Decoder M/R# CS# AB[16:1] DB[15:0]
CLKI2
REDCAP2 BUS
HIOVDD
FPDAT[7:4] FPSHIFT FPFRAME FPLINE DRDY
D[3:0] FPSHIFT
4-bit Single LCD Display
Bias Power
FPFRAME FPLINE MOD
R/W OE EB1 EB0 CLK RESET_OUT VSS *Note: CSn# can be any of CS0-CS4
RD/WR# RD# WE0# WE1# CLKI RESET# AB0
S1D13706
GPO
Figure 3-7: Typical System Diagram (Motorola REDCAP2 Bus)
.
Oscillator
MC68EZ328/ MC68VZ328 DragonBall BUS
A[25:17]
BS# RD/WR# Decoder M/R#
CLKI2
HIOVDD
FPDAT[7:0] FPSHIFT
D[7:0] FPSHIFT
8-bit Single LCD Display
Bias Power
CSX A[16:1] D[15:0]
CS# AB[16:1] DB[15:0]
FPFRAME FPLINE DRDY
FPFRAME FPLINE MOD
S1D13706
GPO
LWE UWE OE DTACK CLKO RESET VSS
WE0# WE1# RD# WAIT# CLKI RESET# AB0
Figure 3-8: Typical System Diagram (Motorola MC68EZ328/MC68VZ328 "DragonBall" Bus)
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4 Pins
4.1 Pinout Diagram - TQFP15 - 100pin
75 VSS
74 FPDAT17
73 FPDAT16
72 FPDAT15
71 FPDAT14
70 FPDAT13
69 FPDAT12
68 FPDAT11
67 FPDAT10
66 FPDAT9
65 FPDAT8
64 FPDAT7
63 NIOVDD
62 VSS
61 FPDAT6
60 FPDAT5
59 FPDAT4
58 FPDAT3
57 FPDAT2
56 FPDAT1
55 FPDAT0
54 FPSHIFT
53 FPLINE
52 FPFRAME
51
COREVDD
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
NIOVDD CLKI2 CNF7 CNF6 CNF5 CNF4 CNF3 CNF2 CNF1 CNF0
VSS DRDY GPO
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
NIOVDD
CVOUT GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 PWMOUT NIOVDD VSS DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 RD/WR# RESET# HIOVDD HIOVDD DB15 DB14 DB13 DB12 DB10 DB11 VSS DB9 WAIT# WE0# WE1# M/R# CLKI RD# VSS CS# AB3 2 AB2 AB1 AB0 BS#
TESTEN AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 VSS COREVDD 1
S1D13706
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Figure 4-1: Pinout Diagram - TQFP15 - 100pin (S1D13706F00A)
Note
Package type: 100 pin surface mount TQFP15
3
4
5
6
7
8
9
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4.2 Pinout Diagram - Die Form
170 165 160 155 150 145 140 135 130 125 120
175
DIE No. X5534D
180
Unusable Pad
115
185
110
190
105
195
Y
100
200
95
205
90
X
210 85
(0,0)
215 80
220
75
225
70
230
65
235
Unusable Pad
60
1
5
10
15
20
25
30
35
40
45
50
55
Figure 4-2: Pinout Diagram - Die Form (S1D13706D00A) Chip Size: 5.88 x 6.55 mm PAD size: 68 x 68 m
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Table 4-1: Pinout Assignments - Die Form (S1D13706D00A)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad No. 1 3 5 8 10 12 15 17 20 22 24 27 29 31 34 36 39 41 43 46 48 50 53 55 58 60 62 65 67 70 72 74 77 79 81 84 86 89 91 93 96 98 100 103 105 108 110 112 115 117 Pin Name LVDD AB3 AB2 AB1 AB0 CS# M/R# BS# RD# WE0# WE1# RD/WR# RESET# VSS CLKI HVDD WAIT# DB15 DB14 DB13 DB12 DB11 DB10 DB9 VSS HVDD DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 VSS HVDD PWMOUT GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0 CVOUT GPO DRDY HVDD VSS X (m) -2331 -2100 -1932 -1680 -1512 -1344 -1092 -924 -672 -504 -336 -84 84 252 504 672 924 1092 1260 1512 1680 1848 2100 2331 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 2813 Y (m) -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -3149 -2478 -2310 -2142 -1890 -1722 -1470 -1302 -1134 -882 -714 -546 -294 -126 126 294 462 714 882 1050 1302 1470 1722 1890 2058 2310 2478 Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pad No. 119 122 124 127 129 131 134 136 139 141 143 146 148 150 153 155 158 160 162 165 167 169 172 174 177 179 181 184 186 189 191 193 196 198 200 203 205 208 210 212 215 217 219 222 224 227 229 231 234 236 Pin Name LVDD FPFRAME FPLINE FPSHIFT FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 VSS HVDD FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT16 FPDAT17 VSS HVDD CLKI2 CNF7 CNF6 CNF5 CNF4 CNF3 CNF2 CNF1 CNF0 TESTEN AB16 AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 AB7 AB6 AB5 AB4 VSS X (m) 2813 2100 1932 1680 1512 1344 1092 924 672 504 336 84 -84 -252 -504 -672 -924 -1092 -1260 -1512 -1680 -1848 -2100 -2331 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 -2813 Y (m) 2667 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 3149 2478 2310 2142 1890 1722 1470 1302 1134 882 714 546 294 126 -126 -294 -462 -714 -882 -1050 -1302 -1470 -1722 -1890 -2058 -2310 -2478
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4.3 Pin Descriptions
Key:
I O IO P LIS LI LB2A LB3P LO3 LB3M T1 Hi-Z = = = = = = = = = = = = Input Output Bi-Directional (Input/Output) Power pin LVTTLa Schmitt input LVTTL input LVTTL IO buffer (6mA/-6mA@3.3V) Low noise LVTTL IO buffer (12mA/-12mA@3.3V) Low noise LVTTL Output buffer (12mA/-12mA@3.3V) Low noise LVTTL IO buffer with input mask (12mA/-12mA@3.3V) Test mode control input with pull-down resistor (typical value of 50 at 3.3V) High Impedance
a
LVTTL is Low Voltage TTL (see Section 5, "D.C. Characteristics" on page 31).
4.3.1 Host Interface
Table 4-2: Host Interface Pin Descriptions
Pin Name Type Pin # Cell IO RESET# Voltage State Description This input pin has multiple functions. * For Generic #1, this pin is not used and should be connected to VSS. * For Generic #2, this pin inputs system address bit 0 (A0). * For SH-3/SH-4, this pin is not used and should be connected to VSS. * For MC68K #1, this pin inputs the lower data strobe (LDS#). * For MC68K #2, this pin inputs system address bit 0 (A0). * For REDCAP2, this pin is not used and should be connected to VSS. * For DragonBall, this pin is not used and should be connected to VSS. See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. AB[16:1] I 87-99, 2-4 LI HIOVDD 0 System address bus bits 16-1.
AB0
I
5
LIS
HIOVDD
0
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Table 4-2: Host Interface Pin Descriptions
Pin Name Type Pin # Cell IO RESET# Voltage State * * * * * Description Input data from the system data bus. For Generic #1, these pins are connected to D[15:0]. For Generic #2, these pins are connected to D[15:0]. For SH-3/SH-4, these pins are connected to D[15:0]. For MC68K #1, these pins are connected to D[15:0]. For MC68K #2, these pins are connected to D[31:16] for a 32bit device (e.g. MC68030) or D[15:0] for a 16-bit device (e.g. MC68340). * For REDCAP2, these pins are connected to D[15:0]. * For DragonBall, these pins are connected to D[15:0]. See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. This input pin has multiple functions. * For Generic #1, this pin inputs the write enable signal for the lower data byte (WE0#). * For Generic #2, this pin inputs the write enable signal (WE#) * For SH-3/SH-4, this pin inputs the write enable signal for data byte 0 (WE0#). * For MC68K #1, this pin must be tied to HIO VDD * For MC68K #2, this pin inputs the bus size bit 0 (SIZ0). * For REDCAP2, this pin inputs the byte enable signal for the D[7:0] data byte (EB1). * For DragonBall, this pin inputs the byte enable signal for the D[7:0] data byte (LWE). See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. This input pin has multiple functions. * For Generic #1, this pin inputs the write enable signal for the upper data byte (WE1#). * For Generic #2, this pin inputs the byte enable signal for the high data byte (BHE#). * For SH-3/SH-4, this pin inputs the write enable signal for data byte 1 (WE1#). * For MC68K #1, this pin inputs the upper data strobe (UDS#). * For MC68K #2, this pin inputs the data strobe (DS#). * For REDCAP2, this pin inputs the byte enable signal for the D[15:8] data byte (EB0). * For DragonBall, this pin inputs the byte enable signal for the D[15:8] data byte (UWE). See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. CS# I 6 LI HIOVDD 1 Chip select input. See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. This input pin is used to select between the display buffer and register address spaces of the S1D13706. M/R# is set high to access the display buffer and low to access the registers. See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary.
DB[15:0]
IO
18-24, 27-35
LB2A
HIOVDD
Hi-Z
WE0#
I
10
LIS
HIOVDD
1
WE1#
I
11
LIS
HIOVDD
1
M/R#
I
7
LIS
HIOVDD
0
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Table 4-2: Host Interface Pin Descriptions
Pin Name Type Pin # Cell IO RESET# Voltage State * * * * * * * Description This input pin has multiple functions. For Generic #1, this pin must be tied to HIO VDD. For Generic #2, this pin must be tied to HIO VDD. For SH-3/SH-4, this pin inputs the bus start signal (BS#). For MC68K #1, this pin inputs the address strobe (AS#). For MC68K #2, this pin inputs the address strobe (AS#). For REDCAP2, this pin must be tied to HIO VDD. For DragonBall, this pin must be tied to HIO VDD.
BS#
I
8
LIS
HIOVDD
1
See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. This input pin has multiple functions. * For Generic #1, this pin inputs the read command for the upper data byte (RD1#). * For Generic #2, this pin must be tied to HIO VDD. * For SH-3/SH-4, this pin inputs the RD/WR# signal. The S1D13706 needs this signal for early decode of the bus cycle. * For MC68K #1, this pin inputs the R/W# signal. * For MC68K #2, this pin inputs the R/W# signal. * For REDCAP2, this pin inputs the R/W signal. * For DragonBall, this pin must be tied to HIO VDD. See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. This input pin has multiple functions. * For Generic #1, this pin inputs the read command for the lower data byte (RD0#). * For Generic #2, this pin inputs the read command (RD#). * For SH-3/SH-4, this pin inputs the read signal (RD#). * For MC68K #1, this pin must be tied to HIO VDD. * For MC68K #2, this pin inputs the bus size bit 1 (SIZ1). * For REDCAP2, this pin inputs the output enable (OE). * For DragonBall, this pin inputs the output enable (OE). See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary.
RD/WR#
I
12
LIS
HIOVDD
1
RD#
I
9
LIS
HIOVDD
1
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Table 4-2: Host Interface Pin Descriptions
Pin Name Type Pin # Cell IO RESET# Voltage State Description During a data transfer, this output pin is driven active to force the system to insert wait states. It is driven inactive to indicate the completion of a data transfer. WAIT# is released to the high impedance state after the data transfer is complete. Its active polarity is configurable. See Table 4-7: "Summary of PowerOn/Reset Options," on page 28. * For Generic #1, this pin outputs the wait signal (WAIT#). * For Generic #2, this pin outputs the wait signal (WAIT#). * For SH-3 mode, this pin outputs the wait request signal (WAIT#). * For SH-4 mode, this pin outputs the device ready signal (RDY#). * For MC68K #1, this pin outputs the data transfer acknowledge signal (DTACK#). * For MC68K #2, this pin outputs the data transfer and size acknowledge bit 1 (DSACK1#). * For REDCAP2, this pin is unused (Hi-Z). * For DragonBall, this pin outputs the data transfer acknowledge signal (DTACK). See Table 4-8: "Host Bus Interface Pin Mapping," on page 29 for summary. RESET# I 13 LIS HIOVDD 0 Active low input to set all internal registers to the default state and to force all signals to their inactive states.
WAIT#
O
17
LB2A
HIOVDD
Hi-Z
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4.3.2 LCD Interface
Table 4-3: LCD Interface Pin Descriptions
Pin Name FPDAT[17:0] Type O Pin # 74-64, 61-55 Cell LB3P IO RESET# Voltage State NIOVDD 0 Panel Data bits 17-0. This output pin has multiple functions. * Frame Pulse * SPS for Sharp HR-TFT * DY for Epson D-TFD See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This output pin has multiple functions. * Line Pulse * LP for Sharp HR-TFT * LP for Epson D-TFD See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This output pin has multiple functions. * Shift Clock * CLK for Sharp HR-TFT * XSCL for Epson D-TFD See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This output pin has multiple functions. * Display enable (DRDY) for TFT panels * 2nd shift clock (FPSHIFT2) for passive LCD with Format 1 interface * GCP for Epson D-TFD * LCD backplane bias signal (MOD) for all other LCD panels See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This pin has multiple functions. * * * * PS for Sharp HR-TFT XINH for Epson D-TFD General purpose IO pin 0 (GPIO0) Hardware Video Invert Description
FPFRAME
O
52
LB3P
NIOVDD
0
FPLINE
O
53
LB3P
NIOVDD
0
FPSHIFT
O
54
LB3P
NIOVDD
0
DRDY
O
48
LO3
NIOVDD
0
GPIO0
IO
45
LB3M
NIOVDD
0
See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This pin has multiple functions. * CLS for Sharp HR-TFT * YSCL for Epson D-TFD * General purpose IO pin 1 (GPIO1) See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary.
GPIO1
IO
44
LB3M
NIOVDD
0
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Table 4-3: LCD Interface Pin Descriptions
Pin Name Type Pin # Cell IO RESET# Voltage State Description This pin has multiple functions. * REV for Sharp HR-TFT * FR for Epson D-TFD * General purpose IO pin 2 (GPIO2) See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This pin has multiple functions. * SPL for Sharp HR-TFT * FRS for Epson D-TFD * General purpose IO pin 3 (GPIO3) See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This pin has multiple functions. GPIO4 IO 41 LB3M NIOVDD 0 * RES for Epson D-TFD * General purpose IO pin 4 (GPIO4) See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This pin has multiple functions. GPIO5 IO 40 LB3M NIOVDD 0 * DD_P1 for Epson D-TFD * General purpose IO pin 5 (GPIO5) See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This pin has multiple functions. GPIO6 IO 39 LB3M NIOVDD 0 * YSCLD for Epson D-TFD * General purpose IO pin 6 (GPIO6) See Table 4-9: "LCD Interface Pin Mapping," on page 30 for summary. This output pin has multiple functions. PWMOUT O 38 LB3P NIOVDD 0 * PWM Clock output * General purpose output This output pin has multiple functions. CVOUT O 46 LB3P NIOVDD 0 * CV Pulse Output * General purpose output
GPIO2
IO
43
LB3M
NIOVDD
0
GPIO3
IO
42
LB3M
NIOVDD
0
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4.3.3 Clock Input
Table 4-4: Clock Input Pin Descriptions
Pin Name CLKI CLKI2 Type I I Pin # 15 77 Cell LI LI IO RESET# Voltage State NIOVDD NIOVDD -- -- Description Typically used as input clock source for bus clock and memory clock Typically used as input clock source for pixel clock
4.3.4 Miscellaneous
Table 4-5: Miscellaneous Pin Descriptions
Pin Name Type Pin # Cell IO RESET# Voltage State Description These inputs are used to configure the S1D13706 - see Table 4-7: "Summary of Power-On/Reset Options," on page 28. Note: These pins are used for configuration of the S1D13706 and must be connected directly to IO VDD or VSS. General Purpose Output (possibly used for controlling the LCD power). It may also be used for the MOD control signal of the Sharp HR-TFT panel. Test Enable input used for production test only (has type 1 pulldown resistor with a typical value of 50 at 3.3V).
CNF[7:0]
I
78-85
LI
NIOVDD
--
GPO
O
47
LO3
NIOVDD
0
TESTEN
I
86
T1
NIOVDD
0
4.3.5 Power And Ground
Table 4-6: Power And Ground Pin Descriptions
Pin Name HIOVDD Type P Pin # 16, 26 37, 49, 63, 76 1, 51 14, 25, 36, 50, 62, 75, 100 Cell P IO RESET# Voltage State -- -- Description IO VDD pins associated with the host interface pins as described in Section 4.3.1, "Host Interface" on page 21. IO VDD pins associated with the non-host interface pins as described in Section 4.3.2, "LCD Interface" on page 25, Section 4.3.3, "Clock Input" on page 27, and Section 4.3.4, "Miscellaneous" on page 27. 2 Core VDD. pins. 7 VSS pins.
NIOVDD COREVDD VSS
P P P
P P P
-- -- --
-- -- --
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4.4 Summary of Configuration Options
These pins are used for configuration of the S1D13706 and must be connected directly to NIOVDD or VSS. The state of CNF[6:0] is latched on the rising edge of RESET#. Changing state at any other time has no effect. Table 4-7: Summary of Power-On/Reset Options
S1D13706 Configuration Input Power-On/Reset State 1 (connected to NIOVDD) Select host bus interface as follows: CNF4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 X CNF2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 CNF1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 CNF0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Host Bus SH-4/SH-3 interface, Big Endian SH-4/SH-3 interface, Little Endian MC68K #1, Big Endian Reserved MC68K #2, Big Endian Reserved Generic #1, Big Endian Generic #1, Little Endian Reserved Generic #2, Little Endian REDCAP2, Big Endian Reserved DragonBall (MC68EZ328/MC68VZ328), Big Endian Reserved Reserved 0 (Connected to VSS)
CNF4,CNF[2:0]
Note: The host bus interface is 16-bit only. CNF3 CNF5 Configure GPIO pins as inputs at power-on WAIT# is active high CLKI to BCLK divide select: CNF[7:6] CNF7 0 0 1 1 CNF6 0 1 0 1 CLKI to BCLK Divide Ratio 1:1 2:1 3:1 4:1 Configure GPIO pins as outputs at power-on (for use by HR-TFT/D-TFD when selected) WAIT# is active low
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4.5 Host Bus Interface Pin Mapping
Table 4-8: Host Bus Interface Pin Mapping
S1D13706 Pin Name AB[16:1] AB0 DB[15:0] CS# M/R# CLKI BS# RD/WR# RD# WE0# WE1# WAIT# RESET# BUSCLK BUSCLK Connected to VDD RD# WE# BHE# WAIT# RESET# CKIO BS# RD/WR# RD# WE0# WE1# WAIT#/ RDY# RESET# Connected to VDD RD1# RD0# WE0# WE1# WAIT# RESET# Generic #1 Generic #2 Hitachi SH-3 /SH-4 A[16:1] A0
1
Motorola MC68K #1 A[16:1] LDS# D[15:0] External Decode CLK AS# R/W# Connected to VDD Connected to VDD UDS# DTACK# RESET#
Motorola MC68K #2 A[16:1] A0 D[15:0]2
Motorola REDCAP2 A[16:1] A0
1
Motorola MC68EZ328/ MC68VZ328 DragonBall A[16:1] A01 D[15:0] CSX CLKO Connected to VDD OE LWE UWE DTACK RESET
A[16:1] A01 D[15:0]
A[16:1] A0 D[15:0]
D[15:0] CSn#
D[15:0] CSn CLK
External Decode
External Decode CLK AS# R/W# SIZ1 SIZ0 DS# DSACK1# RESET#
Connected to VDD R/W OE EB1 EB0 N/A RESET_OUT
Note 1 A0 for these busses is not used internally by the S1D13706 and should be connected to V . SS 2 If the target MC68K bus is 32-bit, then these signals should be connected to D[31:16].
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4.6 LCD Interface Pin Mapping
Table 4-9: LCD Interface Pin Mapping
Monochrome Passive Panel Pin Name 4-bit FPFRAME FPLINE FPSHIFT DRDY FPDAT0 FPDAT1 FPDAT2 FPDAT3 FPDAT4 FPDAT5 FPDAT6 FPDAT7 FPDAT8 FPDAT9 FPDAT10 FPDAT11 FPDAT12 FPDAT13 FPDAT14 FPDAT15 FPDAT16 FPDAT17 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPO CVOUT PWMOUT driven 0 driven 0 driven 0 driven 0 D0 D1 D2 D3 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 MOD D0 D1 D2 D3 D4 D5 D6 D7 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 driven 0 driven 0 driven 0 driven 0 D0 (R2)2 D1 (B1)2 D2 (G1)2 D3 (R1)2 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 FPSHIFT2 D0 (B5)2 D1 (R5)2 D2 (G4)2 D3 (B3)2 D4 (R3)2 D5 (G2)2 D6 (B1)2 D7 (R1)2 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 Single 8-bit 4-bit Color Passive Panel Single Format 1 8-bit Format 2 8-bit FPFRAME FPLINE FPSHIFT MOD D0 (G3)2 D1 (R3)2 D2 (B2)2 D3 (G2)2 D4 (R2)2 D5 (B1)2 D6 (G1)2 D7 (R1)2 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 D0 (R6)2 D1 (G5)2 D2 (B4)2 D3 (R4)2 D8 (B5)2 D9 (R5)2 D10 (G4)2 D11 (B3)2 D4 (G3)2 D5 (B2)2 D6 (R2)2 D7 (G1)2 D12 (R3)2 D13 (G2)2 D14 (B1)2 D15 (R1)2 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 R2 R1 R0 G2 G1 G0 B2 B1 B0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 DRDY R3 R2 R1 G3 G2 G1 B3 B2 B1 R0 driven 0 driven 0 G0 driven 0 driven 0 B0 driven 0 driven 0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 R0 G2 G1 G0 B2 B1 B0 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 16-Bit 9-bit Others 12-bit 18-bit Color TFT Panel Sharp HRTFT1 18-bit SPS LP DCLK no connect R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 R0 G2 G1 G0 B2 B1 B0 PS CLS REV SPL GPIO4 (output only) GPIO5 (output only) GPIO6 (output only) MOD
3
Epson D-TFD1 18-bit DY LP XSCL GCP R5 R4 R3 G5 G4 G3 B5 B4 B3 R2 R1 R0 G2 G1 G0 B2 B1 B0 XINH YSCL FR FRS RES DD_P1 YSCLD GPO
GPO (General Purpose Output) CVOUT PWMOUT
Note
GPIO pins must be configured as outputs (CNF3 = 0 at RESET#) when the HR-TFT or D-TFD interface is selected. 2 These pin mappings use signal names commonly used for each panel type, however signal names may differ between panel manufacturers. The values shown in brackets represent the color components as mapped to the corresponding FPDATxx signals at the first valid edge of FPSHIFT. For further FPDATxx to LCD interface mapping, see Section 6.4, "Display Interface" on page 56. 3 When the HR-TFT interface is selected (REG[10h] bits 1-0 = 10), this GPO can be used to control the HR-TFT MOD signal. Note this is not the same signal as the S1D13706 DRDY(MOD) signal used for passive panels.
1
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5 D.C. Characteristics
Table 5-1: Absolute Maximum Ratings
Symbol Core VDD IO VDD VIN VOUT TSTG TSOL Parameter Supply Voltage Supply Voltage Input Voltage Output Voltage Storage Temperature Solder Temperature/Time VSS - 0.3 to 4.0 VSS - 0.3 to 4.0 VSS - 0.3 to IO VDD + 0.5 VSS - 0.3 to IO VDD + 0.5 -65 to 150 260 for 10 sec. max at lead Rating Units V V V V C C
Table 5-2: Recommended Operating Conditions
Symbol Core VDD HIO VDD NIO VDD VIN TOPR Parameter Supply Voltage Supply Voltage Supply Voltage Input Voltage Operating Temperature Condition VSS = 0 V VSS = 0 V VSS = 0 V 1.8 3.0 1.8 3.0 3.0 VSS -40 25 Min 2.0 3.3 2.0 3.3 3.3 Typ 2.2 3.6 2.2 3.6 3.6 IO VDD 85 Max Units V V V V V V C
Note
The S1D13706 requires that Core VDD HIO VDD and Core VDD NIO VDD.
Table 5-3: Electrical Characteristics for VDD = 3.3V typical
Symbol IDDS IIZ IOZ VOH Parameter Quiescent Current Input Leakage Current Output Leakage Current High Level Output Voltage Condition Quiescent Conditions -1 -1 VDD = min IOH = -6mA (Type 2) -12mA (Type 3) VDD = min IOL = 6mA (Type 2) 12mA (Type 3) LVTTL Level, VDD = max LVTTL Level, VDD = min LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt VI = VDD VDD - 0.4 Min Typ Max 170 1 1 Units A A A V
VOL VIH VIL VT+ VTVH1 RPD CI CO CIO
Low Level Output Voltage High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Hysteresis Voltage Pull Down Resistance Input Pin Capacitance Output Pin Capacitance Bi-Directional Pin Capacitance
0.4 2.0 1.1 0.6 0.1 20 0.8 2.4 1.8 50 120 10 10 10
V V V V V V k pF pF pF
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6 A.C. Characteristics
Conditions: HIO VDD = 2.0V 10% and HIO VDD = 3.3V 10% NIO VDD = 3.3V 10% TA = -40 C to 85 C Trise and Tfall for all inputs must be < 5 nsec (10% ~ 90%) CL = 50pF (Bus/MPU Interface) CL = 0pF (LCD Panel Interface)
6.1 Clock Timing
6.1.1 Input Clocks
Clock Input Waveform
t PWH t PWL
90% V IH VIL 10%
tr
t TOSC
f
Figure 6-1: Clock Input Requirements
Table 6-1: Clock Input Requirements for CLKI when CLKI to BCLK divide > 1
Symbol fOSC TOSC tPWH tPWL tf tr Parameter Input Clock Frequency (CLKI) Input Clock period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI) Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 1/fOSC 4.5 4.5 5 5 2.0V Min Max 40 1/fOSC 4.5 4.5 5 5 Min 3.3V Max 100 Units MHz ns ns ns ns ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI. See Section 6.1.2, "Internal Clocks" on page 34 for internal clock requirements.
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Table 6-2: Clock Input Requirements for CLKI when CLKI to BCLK divide = 1
Symbol fOSC TOSC tPWH tPWL tf tr Parameter Input Clock Frequency (CLKI) Input Clock period (CLKI) Input Clock Pulse Width High (CLKI) Input Clock Pulse Width Low (CLKI) Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 1/fOSC 3 3 5 5 2.0V Min Max 20 1/fOSC 3 3 5 5 Min 3.3V Max 66 Units MHz ns ns ns ns ns
Note
Maximum internal requirements for clocks derived from CLKI must be considered when determining the frequency of CLKI. See Section 6.1.2, "Internal Clocks" on page 34 for internal clock requirements. Table 6-3: Clock Input Requirements for CLKI2
Symbol fOSC TOSC tPWH tPWL tf tr Parameter Input Clock Frequency (CLKI2) Input Clock period (CLKI2) Input Clock Pulse Width High (CLKI2) Input Clock Pulse Width Low (CLKI2) Input Clock Fall Time (10% - 90%) Input Clock Rise Time (10% - 90%) 1/fOSC 3 3 5 5 2.0V Min Max 20 1/fOSC 3 3 5 5 Min 3.3V Max 66 Units MHz ns ns ns ns ns
Note
Maximum internal requirements for clocks derived from CLKI2 must be considered when determining the frequency of CLKI2. See Section 6.1.2, "Internal Clocks" on page 34 for internal clock requirements.
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6.1.2 Internal Clocks
Table 6-4: Internal Clock Requirements
Symbol fBCLK fMCLK fPCLK Bus Clock frequency Memory Clock frequency Pixel Clock frequency Parameter 2.0V Min Max 20 20 20 20 Min 3.3V Max 66 50 50 66 Units MHz MHz MHz MHz
fPWMCLK PWM Clock frequency
Note
For further information on internal clocks, refer to Section 7, "Clocks" on page 90.
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6.2 CPU Interface Timing
The following section includes CPU interface AC Timing for both 2.0V and 3.3V. The 2.0V timings are based on HIO VDD = Core VDD = 2.0V. The 3.3V timings are based on HIO VDD = Core VDD = 3.3V.
6.2.1 Generic #1 Interface Timing
TCLK CLK t3 A[16:1] M/R# t5 CS# t7 RD0#,RD1# WE0#,WE1# t8 t6 t4 t1 t2
t9 WAIT# t11 D[15:0](write) t13 D[15:0](read) t14 VALID t12
t10
t15
Figure 6-2: Generic #1 Interface Timing
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Table 6-5: Generic #1 Interface Timing
Symbol fCLK TCLK t1 t2 t3 t4 t5 t6 t7a t7b t7c t7d t8 t9 t10 t11 t12 t13 t14 t15 Parameter Bus Clock frequency Bus Clock period Clock pulse width high Clock pulse width low A[16:1], M/R# setup to first CLK rising edge where CS# = 0 and either RD0#, RD1# = 0 or WE0#, WE1# = 0 A[16:1], M/R# hold from either RD0#, RD1# or WE0#, WE1# rising edge CS# setup to CLK rising edge CS# hold from either RD0#, RD1# or WE0#, WE1# rising edge RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK / 2 RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK / 3 RD0#, RD1#, WE0#, WE1# asserted for MCLK = BCLK / 4 RD0#, RD1#, WE0#, WE1# setup to CLK rising edge Falling edge of either RD0#, RD1# or WE0#, WE1# to WAIT# driven low Rising edge of either RD0#, RD1# or WE0#, WE1# to WAIT# high impedance D[15:0] setup to third CLK rising edge where CS# = 0 and WE0#, WE1# = 0 (write cycle) (see note 1) D[15:0] hold from WAIT# rising edge (write cycle) RD0#, RD1# falling edge to D[15:0] driven (read cycle) WAIT# rising edge to D[15:0] valid (read cycle) RD0#, RD1# rising edge to D[15:0] high impedance (read cycle) 2.0V Min 1/fCLK 22.5 22.5 1 0 0 0 8.5 11.5 13.5 17.5 2 5 5 1 1 4 3 27 0 29 31 34 1 3 3 0 0 3 3 14 2 11 15 13 Max 20 Min 1/fCLK 9 9 1 0 1 0 8.5 11.5 13.5 17.5 3.3V Max 50 Unit MHz ns ns ns ns ns ns ns TCLK TCLK TCLK TCLK ns ns ns ns ns ns ns ns
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.2.2 Generic #2 Interface Timing (e.g. ISA)
TBUSCLK BUSCLK t3 SA[16:0] M/R#, SBHE# t5 CS# t7 MEMR# MEMW# t8 t6 t4 t1 t2
t9 IOCHRDY t11 SD[15:0] (write) t13 SD[15:0] (read) t14 VALID t12
t10
t15
Figure 6-3: Generic #2 Interface Timing
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Table 6-6: Generic #2 Interface Timing
Symbol fBUSCLK TBUSCLK t1 t2 t3 t4 t5 t6 t7a t7b t7c t7d t8 t9 t10 t11 t12 t13 t14 t15 Parameter 2.0V Min Max 20 Min 1/fBUSCLK 9 9 1 0 1 0 8.5 11.5 13.5 17.5 1 3 3 0 0 3 15 13 8 11 13 17 3.3V Max 50 Unit MHz ns ns ns ns ns ns ns TBUSCLK TBUSCLK TBUSCLK TBUSCLK ns ns ns ns ns ns ns ns
Bus Clock frequency Bus Clock period 1/fBUSCLK Clock pulse width high 22.5 Clock pulse width low 22.5 SA[16:0], M/R#, SBHE# setup to first BUSCLK rising edge 1 where CS# = 0 and either MEMR# = 0 or MEMW# = 0 SA[16:0], M/R#, SBHE# hold from either MEMR# or MEMW# 0 rising edge CS# setup to BUSCLK rising edge 0 CS# hold from either MEMR# or MEMW# rising edge 0 MEMR#/MEMW# asserted for MCLK = BCLK MEMR#/MEMW# asserted for MCLK = BCLK / 2 MEMR#/MEMW# asserted for MCLK = BCLK / 3 MEMR#/MEMW# asserted for MCLK = BCLK / 4 MEMR# or MEMW# setup to BUSCLK rising edge 2 Falling edge of either MEMR# or MEMW# to IOCHRDY driven 5 low Rising edge of either MEMR# or MEMW# to IOCHRDY high 5 impedance SD[15:0] setup to third BUSCLK rising edge where CS# = 0 and 1 MEMW# = 0 (write cycle) (see note 1) SD[15:0] hold from IOCHRDY rising edge (write cycle) 1 MEMR# falling edge to SD[15:0] driven (read cycle) 4 IOCHRDY rising edge to SD[15:0] valid (read cycle) Rising edge of MEMR# to SD[15:0] high impedance (read 5 cycle)
26 0 33
13 2 12
3
1. t11 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.2.3 Hitachi SH-4 Interface Timing
TCKIO CKIO t3 A[16:1], M/R# RD/WR# t5 BS# t7 CSn# t9 t10 WEn# RD# t11 RDY# Hi-Z t15 D[15:0] (write) Hi-Z t17 D[15:0] (read) Hi-Z VALID t18 Hi-Z t16 Hi-Z t12 t13 t14 Hi-Z t8 t6 t4 t1 t2
Figure 6-4: Hitachi SH-4 Interface Timing
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Table 6-7: Hitachi SH-4 Interface Timing
Symbol fCKIO TCKIO t1 t2 t3 t4 t5 t6 t7 t8 t9a t9b t9c t9d t10 t11 t12 t13 t14 t15 t16 t17 t18 Clock frequency Clock period Clock pulse width low Clock pulse width high A[16:1], M/R#, RD/WR# setup to CKIO A[16:1], M/R#, RD/WR# hold from CSn# BS# setup BS# hold CSn# setup CSn# high setup to CKIO RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz) RD# or WEn# asserted for MCLK = BCLK / 2 RD# or WEn# asserted for MCLK = BCLK / 3 RD# or WEn# asserted for MCLK = BCLK / 4 Falling edge RD# to D[15:0] driven (read cycle) Falling edge CSn# to RDY# driven high CKIO to RDY# low CSn# high to RDY# high Falling edge CKIO to RDY# high impedance D[15:0] setup to 2nd CKIO after BS# (write cycle) (see note 1) D[15:0] hold (write cycle) RDY# falling edge to D[15:0] valid (read cycle) Rising edge RD# to D[15:0] high impedance (read cycle) 5 5 3 5 5 5 1 0 0 31 3 1/fCKIO 22.5 22.5 0 0 3 7 0 0 8.5 11.5 13.5 18.5 24 19 42 35 38 3 3 4 4 4 0 0 2 12 Parameter 2.0V Min Max 20 1/fCKIO 6.8 6.8 1 0 1 2 1 2 8.5 11.5 13.5 18.5 12 12 18 14 14 Min 3.3V Max 66 Unit MHz ns ns ns ns ns ns ns ns ns TCKIO TCKIO TCKIO TCKIO ns ns ns ns ns ns ns ns ns
1. t15 is the delay from when data is placed on the bus until the data is latched into the write buffer. Note
Minimum one software WAIT state is required.
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6.2.4 Hitachi SH-3 Interface Timing
TCKIO CKIO t3 A[16:1], M/R# RD/WR# t5 BS# t7 CSn# t9 t10 WEn# RD# t12 WAIT# Hi-Z t14 D[15:0] (write) Hi-Z t16 D[15:0] (read) Hi-Z VALID t17 Hi-Z t15 Hi-Z t13 Hi-Z t11 t8 t6 t4 t1 t2
Figure 6-5: Hitachi SH-3 Interface Timing
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Table 6-8: Hitachi SH-3 Interface Timing
Symbol fCKIO TCKIO t1 t2 t3 t4 t5 t6 t7 t8 t9a t9b t9c t9d t10 t11 t12 t13 t14 t15 t16 t17 Bus Clock frequency Bus Clock period Bus Clock pulse width low Bus Clock pulse width high A[16:1], M/R#, RD/WR# setup to CKIO CSn# high setup to CKIO BS# setup BS# hold CSn# setup A[16:1], M/R#, RD/WR# hold from CS# RD# or WEn# asserted for MCLK = BCLK (max. MCLK = 50MHz) RD# or WEn# asserted for MCLK = BCLK / 2 RD# or WEn# asserted for MCLK = BCLK / 3 RD# or WEn# asserted for MCLK = BCLK / 4 Falling edge RD# to D[15:0] driven (read cycle) Rising edge CSn# to WAIT# high impedance Falling edge CSn# to WAIT# driven low CKIO to WAIT# delay D[15:0] setup to 2
nd
Parameter
2.0V Min 1/fCKIO 22.5 22.5 0 0 3 7 0 0 8.5 11.5 13.5 18.5 5 4 3 6 1 0 0 5 31 3 24 24 24 45 3 2 2 4 0 0 Max 20 Min
3.3V Max 66 1/fCKIO 6.8 6.8 1 1 1 2 1 0 8.5 11.5 13.5 18.5 12 10 12 18
Unit MHz ns ns ns ns ns ns ns ns ns TCKIO TCKIO TCKIO TCKIO ns ns ns ns ns ns
CKIO after BS# (write cycle) (see note 1)
D[15:0] hold (write cycle) WAIT# rising edge to D[15:0] valid (read cycle) Rising edge RD# to D[15:0] high impedance (read cycle)
2 12
ns ns
1. t14 is the delay from when data is placed on the bus until the data is latched into the write buffer. Note
Minimum one software WAIT state is required.
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6.2.5 Motorola MC68K #1 Interface Timing (e.g. MC68000)
TCLK CLK t3 A[16:1] M/R# t5 CS# t7 t8 AS# t10 t11 t12 t9 t6 t4 t1 t2
UDS# LDS# t13 R/W# t15 DTACK#
t14
t16
t17 D[15:0](write) t19 D[15:0](read) t20
t18
t21 VALID
Figure 6-6: Motorola MC68K #1 Interface Timing
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Table 6-9: Motorola MC68K #1 Interface Timing
Symbol fCLK TCLK t1 t2 t3 t4 t5 t6 t7a t7b t7c t7d t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 Bus Clock Frequency Bus Clock period Clock pulse width high Clock pulse width low A[16:1], M/R# setup to first CLK rising edge where CS# = 0, AS# = 0, UDS# = 0, and LDS# = 0 A[16:1], M/R# hold from AS# rising edge CS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 CS# hold from AS# rising edge AS# asserted for MCLK = BCLK AS# asserted for MCLK = BCLK / 2 AS# asserted for MCLK = BCLK / 3 AS# asserted for MCLK = BCLK / 4 AS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 AS# setup to CLK rising edge UDS#/LDS# setup to CLK rising edge while CS#, AS#, UDS#/LDS# = 0 UDS#/LDS# high setup to CLK rising edge First CLK rising edge where AS# = 1 to DTACK# high impedance R/W# setup to CLK rising edge before all CS#, AS#, UDS# and/or LDS# = 0 R/W# hold from AS# rising edge AS# = 0 and CS# = 0 to DTACK# driven high AS# rising edge to DTACK# rising edge D[15:0] valid to third CLK rising edge where CS# = 0, AS# = 0 and either UDS# = 0 or LDS# = 0 (write cycle) (see note 1) D[15:0] hold from DTACK# falling edge (write cycle) UDS# = 0 and/or LDS# = 0 to D[15:0] driven (read cycle) DTACK# falling edge to D[15:0] valid (read cycle) UDS#, LDS# rising edge to D[15:0] high impedance (read cycle) 5 1 1 3 3 5 0 0 4 6 1 0 4 27 0 33 3 23 39 40 1/fCLK 22.5 22.5 1 0 0 0 8 11 13 18 1 2 1 2 3 1 0 3 4 0 0 3 13 2 13 13 16 14 Parameter 2.0V Min Max 20 1/fCLK 9 9 1 0 1 0 8 11 13 18 Min 3.3V Max 50 Unit MHz ns ns ns ns ns ns ns TCLK TCLK TCLK TCLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.2.6 Motorola MC68K #2 Interface Timing (e.g. MC68030)
TCLK CLK t3 A[16:0] M/R#, SIZ[1:0] t6 t5 CS# t7 t8 AS# t11 t10 DS# t13 R/W# t15 DSACK1# t17 D[31:16](write) t19 D[31:16](read) t20 VALID t21 t18 t16 t14 t12 t9 t4 t1 t2
Figure 6-7: Motorola MC68K #2 Interface Timing
Note
For information on the implementation of the Motorola 68K #2 Host Bus Interface, see Interfacing To The Motorola MC68030 Microprocessor, document number X31B-G-013-xx.
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Table 6-10: Motorola MC68K #2 Interface Timing
Symbol fCLK TCLK t1 t2 t3 t4 t5 t6 t7a t7b t7c t7d t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 Bus Clock frequency Bus Clock period Clock pulse width high Clock pulse width low A[16:0], SIZ[1:0], M/R# setup to first CLK rising edge where CS# = 0, AS# = 0, DS# = 0 A[16:0], SIZ[1:0], M/R# hold from AS# rising edge CS# setup to CLK rising edge CS# hold from AS# rising edge AS# asserted for MCLK = BCLK AS# asserted for MCLK = BCLK / 2 AS# asserted for MCLK = BCLK / 3 AS# asserted for MCLK = BCLK / 4 AS# falling edge to CLK rising edge AS# rising edge to CLK rising edge DS# falling edge to CLK rising edge DS# setup to CLK rising edge First CLK where AS# = 1 to DSACK1# high impedance R/W# setup to CLK rising edge before all CS# = 0, AS# = 0, and DS# = 0 R/W# hold from AS# rising edge AS# = 0 and CS# = 0 to DSACK1# rising edge AS# rising edge to DSACK1# rising edge D[31:16] valid to third CLK rising edge where CS# = 0, AS# = 0, and DS# = 0 (write cycle) (see note 1) D[31:16] hold from falling edge of DSACK1# (write cycle) DS# falling edge to D[31:16] driven (read cycle) DSACK1# falling edge to D[31:16] valid (read cycle) DS# rising edge to D[31:16] invalid/high impedance (read cycle) 5 1 1 1 1 5 1 0 4 6 1 0 4 32 0 36 3 23 39 40 1/fCLK 22.5 22.5 1 0 0 0 8 11 13 18 1 3 1 3 3 1 0 3 4 0 0 3 14 2 13 14 17 14 Parameter 2.0V Min Max 20 1/fCLK 9 9 1 0 1 0 8 11 13 18 Min 3.3V Max 50 Unit MHz ns ns ns ns ns ns ns TCLK TCLK TCLK TCLK ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. t17 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.2.7 Motorola REDCAP2 Interface Timing
TCKO CKO t5 M/R# A[16:1] R/W CSn t3 t4 t1 t2
t6 EB0 EB1 (write) D[15:0] (write) OE EB0 EB1 (read) D[15:0] (read) Hi-Z Hi-Z
t7
t8 VALID
t9 Hi-Z
t10 t13 t12 VALID
t11
t14 Hi-Z
Note: CSn may be any of CS0 - CS4.
Figure 6-8: Motorola REDCAP2 Interface Timing
Note
For further information on implementing the REDCAP2 microprocessor, see Interfacing to the Motorola REDCAP2 DSP with Integrated MCU, document number X31B-G-013-xx.
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Table 6-11: Motorola REDCAP2 Interface Timing
Symbol fCKO TCKO t1 t2 t3 t4 t5a t5b t5c t5d t6 t7 t8 t9 t10 t11 t12 t13a t13b t13c t13d t14 Bus Clock frequency Bus Clock period Bus Clock pulse width low Bus Clock pulse width high A[16:1], M/R#, R/W, CSn setup to CKO rising edge A[16:1], M/R#, R/W, CSn hold from CKO rising edge CSn asserted for MCLK = BCLK CSn asserted for MCLK = BCLK / 2 CSn asserted for MCLK = BCLK / 3 CSn asserted for MCLK = BCLK / 4 EB0, EB1 asserted to CKO rising edge (write cycle) EB0, EB1 de-asserted to CKO rising edge (write cycle) D[15:0] input setup to 3rd CKO rising edge after EB0 or EB1 asserted low (write cycle) (see note 1) D[15:0] input hold from 3rd CKO rising edge after EB0 or EB1 asserted low (write cycle) OE, EB0, EB1 setup to CKO rising edge (read cycle) OE, EB0, EB1 hold to CKO rising edge (read cycle) D[15:0] output delay from OE, EB0, EB1 falling edge (read cycle) 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK (read cycle) 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK / 2 (read cycle) 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK / 3 (read cycle) 1st CKO rising edge after EB0 or EB1 asserted low to D[15:0] valid for MCLK = BCLK / 4 (read cycle) CKO rising edge to D[15:0] output in Hi-Z (read cycle) 4 1/fCKO 26 26 1 0 8 10 13 15 1 1 1 23 1 1 4 29 4.5CKO +7 7CKO + 10 8.5CKO +8 9CKO + 11 31 1 Parameter 2.0V Min Max 17 1/fCKO 26 26 1 0 8 10 13 15 1 4 0 8 0 0 3 10 4.5CKO + 20 6.5CKO + 20 9.5CKO + 20 11.5CKO + 20 11 Min 3.3V Max 17 Units MHz ns ns ns ns ns TCKO TCKO TCKO TCKO ns ns ns ns ns ns ns ns ns ns ns ns
1. t8 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.2.8 Motorola DragonBall Interface Timing with DTACK (e.g. MC68EZ328/MC68VZ328)
TCLKO CLKO t3 A[16:1] t5 t6 CSX t8 UWE/LWE (write) t10 OE (read) t11 t9 t7 t4 t1 t2
t12 D[15:0] (write) Hi-Z
t13 Hi-Z
t14 D[15:0] (read) Hi-Z VALID
t15 Hi-Z
t19 t16 DTACK t17 t18
Figure 6-9: Motorola DragonBall Interface with DTACK Timing
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Table 6-12: Motorola DragonBall Interface with DTACK Timing
MC68EZ328 Symbol fCLKO TCLKO t1 t2 t3 t4 t5a t5b t5c t5d t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 Parameter Bus Clock frequency Bus Clock period Clock pulse width high Clock pulse width low A[16:1] setup 1st CLKO when CSX = 0 and either UWE/LWE or OE = 0 A[16:1] hold from CSX rising edge CSX asserted for MCLK = BCLK CSX asserted for MCLK = BCLK / 2 CSX asserted for MCLK = BCLK / 3 CSX asserted for MCLK = BCLK / 4 CSX setup to CLKO rising edge CSX rising edge to CLKO rising edge UWE/LWE falling edge to CLKO rising edge UWE/LWE rising edge to CSX rising edge OE falling edge to CLKO rising edge OE hold from CSX rising edge D[15:0] setup to 3rd CLKO when CSX, UWE/LWE asserted (write cycle) (see note 1) D[15:0] in hold from CSX rising edge (write cycle) Falling edge of OE to D[15:0] driven (read cycle) CLKO rising edge to D[15:0] output Hi-Z (read cycle) CSX falling edge to DTACK driven high DTACK falling edge to D[15:0] valid (read cycle) CSX high to DTACK high CLKO rising edge to DTACK Hi-Z 5 5 0 0 1 0 1 0 1 0 4 4 3 30 21 20 0 34 40 3 1
1/fCLKO
MC68VZ328 2.0V Min
1/fCLKO
2.0V Min Max 16
3.3V Min
1/fCLKO
3.3V Min
1/fCLKO
Unit 33 MHz ns ns ns ns ns 8 11 13 17 TCLKO TCLKO TCLKO TCLKO ns ns ns ns ns ns ns ns 15 12 13 2 16 6 ns ns ns ns ns ns
Max 16
Max 20
Max
28.1 28.1 0 0 8 11 13 17
28.1 28.1 0 0 8 11 13 17 0 0 0 0 1 0 0 0 3 2 3 15 12 13 2 16 6
22.5 22.5 0 0 8 11 13 17 0 0 1 0 1 0 1 0 4 4 3 5 5 30 21 20 0 34 40
13.5 13.5 0 0
0 0 0 0 1 0 0 0 3 2 3 3 1
1. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.2.9 Motorola DragonBall Interface Timing w/o DTACK (e.g. MC68EZ328/MC68VZ328)
TCLKO CLKO t3 A[16:1] t5 t6 CSX t8 UWE/LWE (write) t10 OE (read) t11 t9 t7 t4 t1 t2
t12 D[15:0] (write) Hi-Z
t13 Hi-Z
t15 t14 D[15:0] (read) Hi-Z VALID
t16 Hi-Z
Figure 6-10: Motorola DragonBall Interface without DTACK# Timing
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Table 6-13: Motorola DragonBall Interface without DTACK Timing
MC68EZ328 Symbol fCLKO t1 t2 t3 t4 t5a Parameter Min Bus Clock frequency
1/fCLKO
MC68VZ328 2.0V Min
1/fCLKO
2.0V Max 16 Min
3.3V Max 16
1/fCLKO
3.3V Min
1/fCLKO
Unit 33 MHz ns ns ns ns ns 8 TCLKO
Max 20
Max
TCLKO Bus Clock period Clock pulse width high Clock pulse width low A[16:1] setup 1st CLKO when CSX = 0 and either UWE/LWE or OE = 0 A[16:1] hold from CSX rising edge CSX asserted for MCLK = BCLK (CPU wait state register should be programmed to 4 wait states) CSX asserted for MCLK = BCLK / 2 (CPU wait state register should be programmed to 6 wait states) CSX asserted for MCLK = BCLK / 3 (CPU wait state register should be programmed to 10 wait states) CSX asserted for MCLK = BCLK / 4 (CPU wait state register should be programmed to 12 wait states) CSX setup to CLKO rising edge CSX rising edge setup to CLKO rising edge UWE/LWE setup to CLKO rising edge UWE/LWE rising edge to CSX rising edge OE setup to CLKO rising edge OE hold from CSX rising edge D[15:0] setup to 3rd CLKO after CSX, UWE/LWE asserted (write cycle) (see note 2) CSX rising edge to D[15:0] output Hi-Z (write cycle) Falling edge of OE to D[15:0] driven (read cycle) 1st CLKO rising edge after OE and CSX asserted low to D[15:0] valid for MCLK = BCLK (read cycle) 1st CLKO rising edge after OE and CSX asserted low to D[15:0] valid for MCLK = BCLK / 2 (read cycle) 1st CLKO rising edge after OE and CSX asserted low to D[15:0] valid for MCLK = BCLK / 3 (read cycle) 1st CLKO rising edge after OE and CSX asserted low to D[15:0] valid for MCLK = BCLK / 4 (read cycle) CLKO rising edge to D[15:0] output Hi-Z (read cycle)
28.1 28.1 0 0 8
28.1 28.1 0 0 8
22.5 22.5 0 0 8
13.6 13.6 0 0
t5b
11
11
11
11
TCLKO
t5c
--
Note 1
--
Note 1
13
13
TCLKO
t5d t6 t7 t8 t9 t10 t11 t12 t13 t14 t15a
-- 0 0 1 0 1 0 1 0 4
Note 1
-- 0 0 0 0 1 0 0 0
Note 1
17 0 0 1 0 1 0 1 0 0 0 0 0 1 0 0 0 30
5.5TCLKO +4
17
TCLKO ns ns ns ns ns ns ns ns
30
5.5TCLKO +4
3
15
5.5TCLKO + 20
4
3
15
5.5TCLKO + 20
ns ns
t15b
8TCLKO + 19
8.5TCLKO + 20
8TCLKO + 19
8.5TCLKO + 20
ns
t15c
9.5TCLKO + 17
10.5TCLKO + 20
9.5TCLKO + 17
10.5TCLKO + 20
ns
t15d t16
13TCLKO +9
14.5TCLKO + 20
13TCLKO +9
14.5TCLKO + 20
ns ns
4
21
2
12
4
21
2
12
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1. The MC68EZ328 cannot support the MCLK = BCLK / 3 and MCLK = BCLK / 4 settings without DTACK. 2. t12 is the delay from when data is placed on the bus until the data is latched into the write buffer.
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6.3 LCD Power Sequencing
6.3.1 Passive/TFT Power-On Sequence
GPO* Power Save Mode Enable** (REG[A0h] bit 0) t2 LCD Signals*** t1
*It is recommended to use the general purpose output pin GPO to control the LCD bias power. **The LCD power-on sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 0. ***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-11: Passive/TFT Power-On Sequence Timing
Table 6-14: Passive/TFT Power-On Sequence Timing
Symbol t1 t2 Parameter LCD signals active to LCD bias active Power Save Mode disabled to LCD signals active Min Note 1 0 Max Note 1 20 ns Units
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected. Note
For HR-TFT Power-On/Off sequence information, see Connecting to the Sharp HR-TFT Panels, document number X31B-G-011-xx. For D-TFD Power-On/Off sequence information, see Connecting to the Epson D-TFD Panels, document number X31B-G-012-xx.
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6.3.2 Passive/TFT Power-Off Sequence
t1 GPO* Power Save Mode Enable** (REG[A0h] bit 0) t2 LCD Signals***
*It is recommended to use the general purpose output pin GPO to control the LCD bias power. **The LCD power-off sequence is activated by programming the Power Save Mode Enable bit (REG[A0h] bit 0) to 1. ***LCD Signals include: FPDAT[17:0], FPSHIFT, FPLINE, FPFRAME, and DRDY.
Figure 6-12: Passive/TFT Power-Off Sequence Timing
Table 6-15: Passive/TFT Power-Off Sequence Timing
Symbol t1 t2 Parameter LCD bias deactivated to LCD signals inactive Power Save Mode enabled to LCD signals low Min Note 1 0 Max Note 1 20 ns Units
1. t1 is controlled by software and must be determined from the bias power supply delay requirements of the panel connected.
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6.4 Display Interface
The timing parameters required to drive a flat panel display are shown below. Timing details for each supported panel type are provided in the remainder of this section.
HT HDPS HPS HPW
VPS VDPS VPW
HDP
VT
VDP
Figure 6-13: Panel Timing Parameters
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Table 6-16: Panel Timing Parameter Definition and Register Summary
Symbol HT HDP1 HDPS HPS HPW VT VDP VDPS VPS VPW Description Horizontal Total Horizontal Display Period1 Derived From Units ((REG[12h] bits 6-0) + 1) x 8 ((REG[14h] bits 6-0) + 1) x 8 For STN panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 22) Ts Horizontal Display Period Start Position For TFT panels: ((REG[17h] bits 1-0, REG[16h] bits 7-0) + 5) FPLINE Pulse Start Position (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1 FPLINE Pulse Width (REG[20h] bits 6-0) + 1 Vertical Total (REG[19h] bits 1-0, REG[18h] bits 7-0) + 1 Vertical Display Period (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Vertical Display Period Start Position REG[1Fh] bits 1-0, REG[1Eh] bits 7-0 Lines (HT) FPFRAME Pulse Start Position REG[27h] bits 1-0, REG[26h] bits 7-0 FPFRAME Pulse Width (REG[24h] bits 6-0) + 1
1. For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16. For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8. 2. The following formulas must be valid for all panel timings: HDPS + HDP < HT VDPS + VDP < VT
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6.4.1 Generic STN Panel Timing
VT (= 1 Frame) VPW FPFRAME VDP FPLINE MOD1(DRDY) FPDAT[17:0]
HT (= 1 Line)
HPS FPLINE FPSHIFT 1PCLK MOD2(DRDY) HDPS FPDAT[17:0] HDP
HPW
Figure 6-14: Generic STN Panel Timing
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VT VPS VPW VDPS VDP HT HPS HPW HDPS HDP
= Vertical Total = [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines = FPFRAME Pulse Start Position = 0 lines, because (REG[27h] bits 1-0, REG[26h] bits 7-0) = 0 = FPFRAME Pulse Width = [(REG[24h] bits 2-0) + 1] lines = Vertical Display Period Start Position = 0 lines, because (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) = 0 = Vertical Display Period = [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines = Horizontal Total = [((REG[12h] bits 6-0) + 1) x 8] pixels = FPLINE Pulse Start Position = [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels = FPLINE Pulse Width = [(REG[20h] bits 6-0) + 1] pixels = Horizontal Display Period Start Position = 22 pixels, because (REG[17h] bits 1-0, REG[16h] bits 7-0) = 0 = Horizontal Display Period = [((REG[14h] bits 6-0) + 1) x 8] pixels
*For passive panels, the HDP must be a minimum of 32 pixels and must be increased by multiples of 16. *HPS must comply with the following formula: HPS > HDP + 22 HPS + HPW < HT *Panel Type Bits (REG[10h] bits 1-0) = 00b (STN) *FPFRAME Pulse Polarity Bit (REG[24h] bit 7) = 1 (active high) *FPLINE Polarity Bit (REG[20h] bit 7) = 1 (active high) *MOD1 is the MOD signal when (REG[11h] bits 5-0) = 0 (MOD toggles every FPFRAME) *MOD2 is the MOD signal when (REG[11h] bits 5-0) = n (MOD toggles every n FPLINE)
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6.4.2 Single Monochrome 4-Bit Panel Timing
VDP VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:4]
Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HDP HNDP
FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4
Invalid Invalid Invalid Invalid 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-317 1-318 1-319 1-320 Invalid Invalid Invalid Invalid
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel
Figure 6-15: Single Monochrome 4-Bit Panel Timing
VDP VNDP = Vertical Display Period = (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines = Vertical Non-Display Period = VT - VDP = (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines = Horizontal Display Period = ((REG[14h] bits 6-0) + 1) x 8Ts = Horizontal Non-Display Period = HT - HDP = (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
HDP HNDP
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Sync Timing FPFRAME
t1
t2
t4 FPLINE t5 DRDY (MOD) Data Timing FPLINE t6 t8 t7 FPSHIFT t12 FPDAT[7:4] t14
t3
t9 t11 t10
t13 1 2
Figure 6-16: Single Monochrome 4-Bit Panel A.C. Timing
Table 6-17: Single Monochrome 4-Bit Panel A.C. Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high FPDAT[7:4] setup to FPSHIFT falling edge FPDAT[7:4] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 note 3 note 4 note 5 note 6 note 7 t6 + t4 t14 + 2 4 2 2 1 2 note 8 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6. 7. 8.
Ts t1min t2min t3min t4min t5min t6min t14min
= pixel clock period = HPS + t4min = t3min - (HPS + t4min) = HT = HPW = HPS - 1 = HPS - (HDP + HDPS) + 2, if negative add t3min = HDPS - (HPS + t4min), if negative add t3min
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6.4.3 Single Monochrome 8-Bit Panel Timing
VDP VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:0]
Invalid LINE1 LINE2 LINE3 LINE4 LINE479 LINE480 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HDP HNDP
FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 1-1 1-2 1-3 1-4 1-5 1-6 1-7 1-8 1-9 1-10 1-11 1-12 1-13 1-14 1-15 1-16 1-633 1-634 1-635 1-636 1-637 1-638 1-639 1-640 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
* Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
Figure 6-17: Single Monochrome 8-Bit Panel Timing
VDP VNDP = Vertical Display Period = (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines = Vertical Non-Display Period = VT - VDP = (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines = Horizontal Display Period = ((REG[14h] bits 6-0) + 1) x 8Ts = Horizontal Non-Display Period = HT - HDP = (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
HDP HNDP
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Sync Timing FPFRAME
t1
t2
t4 FPLINE t5 DRDY (MOD) Data Timing FPLINE t6 t8 t7 FPSHIFT t12 FPDAT[7:0] 1 t14
t3
t9 t11 t10
t13 2
Figure 6-18: Single Monochrome 8-Bit Panel A.C. Timing
Table 6-18: Single Monochrome 8-Bit Panel A.C. Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 note 3 note 4 note 5 note 6 note 7 t6 + t4 t14 + 4 8 4 4 4 4 note 8 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6. 7. 8.
Ts t1min t2min t3min t4min t5min t6min t14min
= pixel clock period = HPS + t4min = t3min - (HPS + t4min) = HT = HPW = HPS - 1 = HPS - (HDP + HDPS) + 4, if negative add t3min = HDPS - (HPS + t4min), if negative add t3min
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6.4.4 Single Color 4-Bit Panel Timing
VDP VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:4]
Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HDP .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts .5Ts 2.5Ts .5Ts .5Ts .5Ts .5Ts
HNDP .5Ts
FPSHIFT
Invalid Invalid Invalid Invalid
.5Ts
.5Ts
.5Ts
.5Ts
FPDAT7 FPDAT6 FPDAT5
Notes:
1-R1 1-G1 1-B1 1-R2
1-G2 1-B2 1-R3 1-G3
1-B3 1-R4 1-G4 1-B4
1-B319 1-R320 1-G320 1-B320
Invalid Invalid Invalid Invalid
FPDAT4
- FPSHIFT uses extended low states in order to process 8 pixels in 6 FPSHIFT clocks - Ts = Pixel clock period (PCLK) - Diagram drawn with 2 FPLINE vertical blank period - Example timing for a 320x240 panel
Figure 6-19: Single Color 4-Bit Panel Timing
VDP VNDP = Vertical Display Period = (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines = Vertical Non-Display Period = VT - VDP = (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines = Horizontal Display Period = ((REG[14h] bits 6-0) + 1) x 8Ts = Horizontal Non-Display Period = HT - HDP = (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
HDP HNDP
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Sync Timing FPFRAME
t1
t2
t4 FPLINE t5 DRDY (MOD) Data Timing FPLINE t6 t8 t7 FPSHIFT t12 FPDAT[7:4] t14
t3
t9 t11 t10
t13 1 2
Figure 6-20: Single Color 4-Bit Panel A.C. Timing
Table 6-19: Single Color 4-Bit Panel A.C. Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high FPDAT[7:4] setup to FPSHIFT falling edge FPDAT[7:4] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 note 3 note 4 note 5 note 6 note 7 t6 + t4 t14 + 0.5 1 0.5 0.5 0.5 0.5 note 8 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6. 7. 8.
Ts t1min t2min t3min t4min t5min t6min t14min
= pixel clock period = HPS + t4min = t3min - (HPS + t4min) = HT = HPW = HPS - 1 = HPS - (HDP + HDPS) + 1.5), if negative add t3min = HDPS - (HPS + t4min) + 1, if negative add t3min
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6.4.5 Single Color 8-Bit Panel Timing (Format 1)
VDP VNDP
FPFRAME FPLINE FPDAT[7:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE239
LINE240
Invalid
LINE1
LINE2
FPLINE
HDP HNDP 2Ts 2Ts 2Ts 2Ts 2Ts 2Ts 2Ts 4Ts 4Ts 2Ts 2Ts 2Ts 2Ts
1R316 1B316 1G317 1R318 1B318 1G319 1R320 1B320
FPSHIFT FPSHIFT2
2Ts
2Ts 4Ts 4Ts 2Ts
2Ts 2Ts 2Ts 2Ts
4Ts 2Ts 2Ts 4Ts
2Ts 4Ts 4Ts 2Ts
2Ts
2Ts
2Ts 2Ts
2Ts Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Notes:
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
1-R1
1-G1
1-G6
1-B6
1-B11
1-R12
1-B1
1-R2
1-R7
1-G7
1-G12
1-B12
1-G2
1-B2
1-B7
1-R8
1-R13
1-G13
1-R3
1-G3
1-G8
1-B8
1-B13
1-R14
1-B3
1-R4
1-R9
1-G9
1-G14
1-B14
1-G4
1-B4
1-B9
1-R10
1-R15
1-G15
1-R5
1-G5
1-G10
1-B10
1-B15
1-R16
1-B5
1-R6
1-R11
1-G11
1-G16
1-B16
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 6 FPSHIFT/FPSHIFT2 rising edges - Ts = Pixel clock period (PCLK) - Diagram drawn with 2 FPLINE vertical blank period - Example timing for a 320x240 panel
Figure 6-21: Single Color 8-Bit Panel Timing (Format 1)
VDP VNDP = Vertical Display Period = (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines = Vertical Non-Display Period = VT - VDP = (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines = Horizontal Display Period = ((REG[14h] bits 6-0) + 1) x 8Ts = Horizontal Non-Display Period = HT - HDP = (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
HDP HNDP
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Sync Timing FPFRAME
t1
t2
t4 FPLINE Data Timing
t3
FPLINE t6a t6b t7a FPSHIFT t7b FPSHIFT2
t12 t13 t12 t13
t8 t14 t11
t9 t10
FPDAT[7:0]
1
2
Figure 6-22: Single Color 8-Bit Panel A.C. Timing (Format 1)
Table 6-20: Single Color 8-Bit Panel A.C. Timing (Format 1)
Symbol t1 t2 t3 t4 t6a t6b t7a t7b t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width FPSHIFT falling edge to FPLINE rising edge FPSHIFT2 falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPSHIFT2 falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT rising, FPSHIFT2 falling edge FPSHIFT2, FPSHIFT period FPSHIFT2, FPSHIFT pulse width low FPSHIFT2, FPSHIFT pulse width high FPDAT[7:0] setup to FPSHIFT2, FPSHIFT falling edge FPDAT[7:0] hold from FPSHIFT2, FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 note 3 note 4 note 5 note 6 note 7 t6a + t4 t6b + t4 t14 + 2 4 2 2 1 1 note 8 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
6
1. 2. 3. 4. 5. 6. 7. 8.
Ts t1min t2min t3min t4min t6amin t6bmin t14min
= pixel clock period = HPS + t4min = t3min - (HPS + t4min) = HT = HPW = HPS - (HDP + HDPS), if negative add t3min = HPS - (HDP + HDPS) + 2, if negative add t3min = HDPS - (HPS + t4min), if negative add t3min
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6.4.6 Single Color 8-Bit Panel Timing (Format 2)
VDP VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[7:0]
Invalid LINE1 LINE2 LINE3 LINE4 LINE239 LINE240 Invalid LINE1 LINE2
FPLINE DRDY (MOD)
HDP
HNDP 2Ts Ts Ts Ts 1-G318 1-B318 1-R319 1-G319 1-B319 1-R320 1-G320 1-B320 Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid 2Ts
FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Notes:
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
2Ts Ts 1-R1 1-G1 1-B1 1-R2 1-G2 1-B2 1-R3 1-G3
Ts Ts 1-B3 1-R4 1-G4 1-B4 1-R5 1-G 5 1-B5 1-R6
2Ts Ts 1-G6 1-B6 1-R7 1-G7 1-B7 1-R8 1-G8 1-B8
2Ts Ts
Ts Ts
2Ts
- The duty cycle of FPSHIFT changes in order to process 8 pixels in 3 FPSHIFT rising clocks - Ts = Pixel clock period (PCLK) - Diagram drawn with 2 FPLINE vertical blank period - Example timing for a 320x240 panel
Figure 6-23: Single Color 8-Bit Panel Timing (Format 2)
VDP VNDP = Vertical Display Period = (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines = Vertical Non-Display Period = VT - VDP = (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines = Horizontal Display Period = ((REG[14h] bits 6-0) + 1) x 8Ts = Horizontal Non-Display Period = HT - HDP = (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
HDP HNDP
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Sync Timing FPFRAME
t1
t2
t4 FPLINE t5 DRDY (MOD) Data Timing FPLINE t6 t8 t7 FPSHIFT t12 FPDAT[7:0] t14
t3
t9 t11 t10
t13 1 2
Figure 6-24: Single Color 8-Bit Panel A.C. Timing (Format 2)
Table 6-21: Single Color 8-Bit Panel A.C. Timing (Format 2)
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high FPDAT[7:0] setup to FPSHIFT falling edge FPDAT[7:0] hold to FPSHIFT falling edge FPLINE falling edge to FPSHIFT rising edge Min note 2 note 3 note 4 note 5 note 6 note 7 t6 + t4 t14 + 2 2 1 1 1 1 note 8 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6. 7. 8.
Ts t1min t2min t3min t4min t5min t6min t14min
= pixel clock period = HPS + t4min = t3min - (HPS + t4min) = HT = HPW = HPS - 1 = HPS - (HDP + HDPS) + 1, if negative add t3min = HDPS - (HPS + t4min), if negative add t3min
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6.4.7 Single Color 16-Bit Panel Timing
VDP VNDP
FPFRAME FPLINE DRDY (MOD) FPDAT[15:0]
Invalid
LINE1
LINE2
LINE3
LINE4
LINE479
LINE480
Invalid
LINE1
LINE2
FPLINE DRDY (MOD)
HDP HNDP 3Ts 2Ts 3Ts 2Ts 3Ts 3Ts 1-G635 1-G636 1-R637 1-B637 1-G638 1-R639 1-B639 1-G640 1-R636 1-B636 1-G637 1-R638 1-B638 1-G639 1-R640 1-B640 3Ts
FPSHIFT FPDAT15 FPDAT14 FPDAT13 FPDAT12 FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT11 FPDAT10 FPDAT9 FPDAT8 FPDAT3 FPDAT2 FPDAT1 FPDAT0
Notes:
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
3Ts 3Ts 1-R1 1-B1 1-G2 1-R3 1-B3 1-G4 1-R5 1-B5 1-G1 1-R2 1-B2 1-G3 1-R4 1-B4 1-G5 1-R6
2Ts
3Ts
3Ts 3Ts
2Ts 3Ts
3Ts 2Ts
3Ts
3Ts 2Ts 1-G6 1-B11 1-R7 1-B7 1-G8 1-R9 1-B9 1-G10 1-R11 1-B6 1-G7 1-R8 1-B8 1-G9 1-R10 1-B10 1-G11 1-G12 1-R13 1-B13 1-G14 1-R15 1-B15 1-G16 1-R12 1-B12 1-G13 1-R14 1-B14 1-G15 1-R16 1-B16
Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid Invalid
- The duty cycle of FPSHIFT changes in order to process 16 pixels in 3 FPSHIFT rising clocks - Ts = Pixel clock period (PCLK) - Diagram drawn with 2 FPLINE vertical blank period - Example timing for a 640x480 panel
Figure 6-25: Single Color 16-Bit Panel Timing
VDP VNDP = Vertical Display Period = (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1 Lines = Vertical Non-Display Period = VT - VDP = (REG[19h] bits 1-0, REG[18h] bits 7-0) - (REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) Lines = Horizontal Display Period = ((REG[14h] bits 6-0) + 1) x 8Ts = Horizontal Non-Display Period = HT - HDP = (((REG[12h] bits 6-0) + 1) x 8Ts) - (((REG[14h] bits 6-0) + 1) x 8Ts)
HDP HNDP
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Sync Timing FPFRAME
t1
t2
t4 FPLINE t5 DRDY (MOD) Data Timing FPLINE t6 t8 t7 FPSHIFT t12 FPDAT[15:0] t14
t3
t9 t11 t10
t13 1 2
Figure 6-26: Single Color 16-Bit Panel A.C. Timing
Table 6-22: Single Color 16-Bit Panel A.C. Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter FPFRAME setup to FPLINE falling edge FPFRAME hold from FPLINE falling edge FPLINE period FPLINE pulse width MOD transition to FPLINE rising edge FPSHIFT falling edge to FPLINE rising edge FPSHIFT falling edge to FPLINE falling edge FPLINE falling edge to FPSHIFT falling edge FPSHIFT period FPSHIFT pulse width low FPSHIFT pulse width high FPDAT[15:0] setup to FPSHIFT rising edge FPDAT[15:0] hold to FPSHIFT rising edge FPLINE falling edge to FPSHIFT rising edge Min note 2 note 3 note 4 note 5 note 6 note 7 t6 + t4 t14 + 3 5 2 2 2 2 note 8 Typ Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6. 7. 8.
Ts t1min t2min t3min t4min t5min t6min t14min
= pixel clock period = HPS + t4min = t3min - (HPS + t4min) = HT = HPW = HPS - 1 = HPS - (HDP + HDPS) + 2, if negative add t3min = HDPS - (HPS + t4min), if negative add t3min
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6.4.8 Generic TFT Panel Timing
VT (= 1 Frame) VPS FPFRAME VDPS FPLINE VDP VPW
DRDY FPDAT[17:0]
HT (= 1 Line) HPS FPLINE FPSHIFT DRDY HDPS FPDAT[17:0] invalid HDP invalid HPW
Figure 6-27: Generic TFT Panel Timing
VT VPS VPW VDPS VDP HT HPS HPW HDPS HDP = Vertical Total = FPFRAME Pulse Start Position = FPFRAME Pulse Width = Vertical Display Period Start Position = Vertical Display Period = Horizontal Total = FPLINE Pulse Start Position = FPLINE Pulse Width = Horizontal Display Period Start Position = Horizontal Display Period = [(REG[19h] bits 1-0, REG[18h] bits 7-0) + 1] lines = (REG[27h] bits 1-0, REG[26h] bits 7-0) lines = [(REG[24h] bits 2-0) + 1] lines = (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0) lines = [(REG[1Dh] bits 1-0, REG[1Ch] bits 7-0) + 1] lines = [((REG[12h] bits 6-0) + 1) x 8] pixels = [(REG[23h] bits 1-0, REG[22h] bits 7-0) + 1] pixels = [(REG[20h] bits 6-0) + 1] pixels = [(REG[17h] bits 1-0, REG[16h] bits 7-0) + 5] pixels = [((REG[14h] bits 6-0) + 1) x 8] pixels
*For TFT panels, the HDP must be a minimum of 8 pixels and must be increased by multiples of 8. *Panel Type Bits (REG[10h] bits 1-0) = 01 (TFT) *FPLINE Pulse Polarity Bit (REG[24h] bit 7) = 0 (active low) *FPFRAME Polarity Bit (REG[20h] bit 7) = 0 (active low)
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6.4.9 9/12/18-Bit TFT Panel Timing
VNDP2 VDP VNDP1
FPFRAME FPLINE FPDAT[17:0] DRDY
LINE240 LINE1 LINE480
FPLINE
HNDP1 HDP HNDP2
FPSHIFT DRDY
FPDAT[17:0]
invalid
1-1
1-2
1-320
invalid
Note: DRDY is used to indicate the first pixel Example Timing for 18-bit 320x240 panel
Figure 6-28: 18-Bit TFT Panel Timing
VDP VNDP = Vertical Display Period = VDP Lines = Vertical Non-Display Period = VNDP1 + VNDP2 = VT - VDP Lines = Vertical Non-Display Period 1 = VNDP - VNDP2 Lines = Vertical Non-Display Period 2 = VDPS - VPS Lines = Horizontal Display Period = HDP Ts = Horizontal Non-Display Period = HNDP1 + HNDP2 = HT - HDP Ts = Horizontal Non-Display Period 1 = HDPS - HPS Ts = Horizontal Non-Display Period 2 = HPS - (HDP + HDPS) Ts
VNDP1 VNDP2 HDP HNDP
if negative add VT
HNDP1 HNDP2
if negative add HT if negative add HT
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t1 t2 FPFRAME t3 FPLINE
t4
FPLINE t5 t6 DRDY t9 t10 t11 FPSHIFT t12 t13 t14 t7 t8
t15 t16 FPDAT[17:0] invalid 1 2 319 320 invalid
Note: DRDY is used to indicate the first pixel
Figure 6-29: TFT A.C. Timing
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Table 6-23: TFT A.C. Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 Parameter FPFRAME cycle time FPFRAME pulse width low FPFRAME falling edge to FPLINE falling edge phase difference FPLINE cycle time FPLINE pulse width low FPLINE Falling edge to DRDY active DRDY pulse width DRDY falling edge to FPLINE falling edge FPSHIFT period FPSHIFT pulse width high FPSHIFT pulse width low FPLINE setup to FPSHIFT falling edge DRDY to FPSHIFT falling edge setup time DRDY hold from FPSHIFT falling edge Data setup to FPSHIFT falling edge Data hold from FPSHIFT falling edge Min VT VPW HPS HT HPW note 2 HDP note 3 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Typ Max Units Lines Lines Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
250
1. Ts 2. t6min 3. t8min
= pixel clock period = HDPS - HPS = HPS - (HDP + HDPS)
if negative add HT if negative add HT
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6.4.10 160x160 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ031B1DDxx)
FPFRAME (SPS) FPLINE (LP) t2 t3 FPLINE (LP) FPSHIFT (CLK) t5 t6 FPDAT[17:0] t7 t9 GPIO3 (SPL) t11 GPIO1 (CLS) t12 GPIO0 (PS) t10 D1 D2 D3 t8 D160
t1
t4
t13
GPIO2 (REV)
Figure 6-30: 160x160 Sharp `Direct' HR-TFT Panel Horizontal Timing
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Table 6-24: 160x160 Sharp `Direct' HR-TFT Horizontal Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Parameter FPLINE start position Horizontal total period FPLINE width FPSHIFT period Data setup to FPSHIFT rising edge Data hold from FPSHIFT rising edge Horizontal display start position Horizontal display period FPLINE rising edge to GPIO3 rising edge GPIO3 pulse width GPIO1(GPIO0) pulse width GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge GPIO2 toggle edge to FPLINE rise edge Min 180 2 1 0.5 0.5 5 160 4 1 136 4 10 Typ 13 Max 220 Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6.
Ts t1typ t2typ t3typ t7typ t8typ
= pixel clock period = (REG[22h] bits 7-0) + 1 = ((REG[12h] bits 6-0) + 1) x 8 = (REG[20h] bits 6-0) + 1 = ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1) = ((REG[14h] bits 6-0) + 1) x 8
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t1 t2 FPDAT[17:0] t4 FPFRAME (SPS) t5 GPIO1 (CLS) t7 GPIO0 (PS) t9 FPLINE (LP) FPSHIFT (CLK) t10 GPIO1 (CLS) t13 t14 GPIO0 (PS) t8 t6
LINE1 LINE2
t3
LINE160
t11
t12
Figure 6-31: 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing
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Table 6-25: 160x160 Sharp `Direct' HR-TFT Panel Vertical Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter Vertical total period Vertical display start position Vertical display period Vertical sync pulse width FPFRAME falling edge to GPIO1 alternate timing start GPIO1 alternate timing period FPFRAME falling edge to GPIO0 alternate timing start GPIO0 alternate timing period GPIO1 first pulse rising edge to FPLINE rising edge GPIO1 first pulse width GPIO1 first pulse falling edge to second pulse rising edge GPIO1 second pulse width GPIO0 falling edge to FPLINE rising edge GPIO0 low pulse width Min 203 Typ 40 160 2 5 4 40 162 4 48 40 48 4 24 Max 264 Units Lines Lines Lines Lines Lines Lines Lines Lines Ts (note 1) Ts Ts Ts Ts Ts
1. Ts
= pixel clock period
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6.4.11 320x240 Sharp `Direct' HR-TFT Panel Timing (e.g. LQ039Q2DS01)
FPFRAME (SPS) FPLINE (LP) t2 t3 FPLINE (LP) FPSHIFT (CLK) t5 t6 FPDAT[17:0] t7 t9 GPIO3 (SPL) t11 GPIO1 (CLS) t12 GPIO0 (PS) D1 D2 D3 t8 D320
t1
t4
t10
t13
GPIO2 (REV)
Figure 6-32: 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing
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Table 6-26: 320x240 Sharp `Direct' HR-TFT Panel Horizontal Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Parameter FPLINE start position Horizontal total period FPLINE width FPSHIFT period Data setup to FPSHIFT rising edge Data hold from FPSHIFT rising edge Horizontal display start position Horizontal display period FPLINE rising edge to GPIO3 rising edge GPIO3 pulse width GPIO1(GPIO0) pulse width GPIO1 rising edge (GPIO0 falling edge) to FPLINE rise edge GPIO2 toggle edge to FPLINE rise edge Min 400 1 1 0.5 0.5 60 320 59 1 353 5 11 Typ 14 Max 440 Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. 2. 3. 4. 5. 6.
Ts t1typ t2typ t3typ t7typ t8typ
= pixel clock period = (REG[22h] bits 7-0) + 1 = ((REG[12h] bits 6-0) + 1) x 8 = (REG[20h] bits 6-0) + 1 = ((REG[16h] bits 7-0) + 5) - ((REG[22h] bits 7-0) + 1) = ((REG[14h] bits 6-0) + 1) x 8
t1 t2 FPDAT[17:0] t4 FPFRAME (SPS)
LINE1 LINE2
t3
LINE240
Figure 6-33: 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing
Table 6-27: 320x240 Sharp `Direct' HR-TFT Panel Vertical Timing
Symbol t1 t2 t3 t4 Parameter Vertical total period Vertical display start position Vertical display period Vertical sync pulse width Min 245 Typ 4 240 2 Max 330 Units Lines Lines Lines Lines
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6.4.12 160x240 Epson D-TFD Panel Timing (e.g. LF26SCR)
t1 FPLINE (LP) t2 FPSHIFT (XSCL) t4 FPDAT[17:0] (R,G,B) t7 t9 t10 GPIO4 (RES) t11 GPIO1 (YSCL) t13 GPIO0 (XINH) t14 GPIO6 (YSCLD) GPIO2 (FR) t16 GPIO3 (FRS) t17 GPIO5 (DD_P1) t17 t15 t12 t11 t12 t10 t8 t9
1 2 3 4
t3
t5
160
t6
Figure 6-34: 160x240 Epson D-TFD Panel Horizontal Timing
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Table 6-28: 160x240 Epson D-TFD Panel Horizontal Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Parameter FPLINE pulse width FPLINE falling edge to FPSHIFT start position FPSHIFT active period FPSHIFT start to first data Horizontal display period Last data to FPSHIFT inactive FPLINE falling edge to GPIO4 first pulse falling edge Horizontal total period GPIO4 first pulse falling edge to second pulse falling edge GPIO4 pulse width GPIO1 pulse width GPIO1 low period GPIO0 pulse width GPIO6 low pulse width GPIO6 rising edge to GPIO0 falling edge GPIO2 toggle to GPIO3 toggle GPIO5 low pulse width Min Typ 9 8.5 167 4 160 3 1 400 200 11 100 100) 200 90 10 1 7 Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. Ts
= pixel clock period
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t1 GPIO4 (RES) t2 DRDY (GCP)
GCP Data Register (REG[2Ch])
1 bit7
1
0
1
0
0
1
0 bit0 bit7 Index 01h
1 bit7
1
Index 00h
Index 00h
Figure 6-35: 160x240 Epson D-TFD Panel GCP Horizontal Timing
Table 6-29: 160x240 Epson D-TFD Panel GCP Horizontal Timing
Symbol t1 t2 Parameter Half of the horizontal total period GCP clock period Min Typ 200 1 Max Units Ts (note 1) Ts
1. Ts
= pixel clock period
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Vertical Total = 250HT t1 FPFRAME (DY) t2 GPIO1 (YSCL) GPIO0 (XINH) t3 FPDAT[17:0] (R,G,B) line1 line2
GPIO2 (FR) (odd frame)
GPIO2 (FR) (even frame)
Figure 6-36: 160x240 Epson D-TFD Panel Vertical Timing Table 6-30: 160x240 Epson D-TFD Panel Vertical Timing
Symbol t1 t2 t3 FPFRAME pulse width Horizontal total period Vertical display start Parameter Min Typ 200 400 400 Max Units Ts (note 1) Ts Ts
1. Ts
= pixel clock period
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6.4.13 320x240 Epson D-TFD Panel Timing (e.g. LF37SQR)
t1 FPLINE (LP) t2 FPSHIFT (XSCL) t4 FPDAT[17:0] (R,G,B) t7 t9 t10 GPIO4 (RES) t11 GPIO1 (YSCL) t13 GPIO0 (XINH) t14 GPIO6 (YSCLD) GPIO2 (FR) t16 GPIO3 (FRS) t17 GPIO5 (DD_P1) t17 t15 t12 t11 t12 t10
1 2 3 4
t3
t5
320
t6
t8 t9
Figure 6-37: 320x240 Epson D-TFD Panel Horizontal Timing
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Table 6-31: 320x240 Epson D-TFD Panel Horizontal Timing
Symbol t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Parameter FPLINE pulse width FPLINE falling edge to FPSHIFT start position FPSHIFT active period FPSHIFT start to first data Horizontal display period Last data to FPSHIFT inactive FPLINE falling edge to GPIO4 first pulse falling edge Horizontal total period GPIO4 first pulse falling edge to second pulse falling edge GPIO4 pulse width GPIO1 pulse width GPIO1 low period GPIO0 pulse width GPIO6 low pulse width GPIO6 rising edge to GPIO0 falling edge GPIO2 toggle to GPIO3 toggle GPIO5 low pulse width Min Typ 9 8.5 331 6 320 5 1 400 200 11 100 100 200 90 10 1 7 Max Units Ts (note 1) Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts Ts
1. Ts
= pixel clock period
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t1 GPIO4 (RES)
t2 DRDY (GCP)
GCP Data Register (REG[2Ch])
1 bit7
1
0
1
0
0
1
0 bit0 bit7 Index 01h
1
1 Index 00h
bit7
Index 00h
Figure 6-38: 320x240 Epson D-TFD Panel GCP Horizontal Timing
Table 6-32: 320x240 Epson D-TFD Panel GCP Horizontal Timing
Symbol t1 t2 Parameter Half of the horizontal total period GCP clock period Min Typ 200 1 Max Units Ts (note 1) Ts
1. Ts
= pixel clock period
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Vertical Total = 250HT t1 FPFRAME (DY) GPIO1 (YSCL) GPIO0 (XINH) t3 FPDAT[17:0] (R,G,B) line1 line2
t2
GPIO2 (FR) (odd frame)
GPIO2 (FR) (even frame)
Figure 6-39: 320x240 Epson D-TFD Panel Vertical Timing Table 6-33: 320x240 Epson D-TFD Panel Vertical Timing
Symbol t1 t2 t3 FPFRAME pulse width Horizontal total period Vertical display start Parameter Min Typ 200 400 400 Max Units Ts (note 1) Ts Ts
1. Ts
= pixel clock period
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7 Clocks
7.1 Clock Descriptions
7.1.1 BCLK
BCLK is an internal clock derived from CLKI. BCLK can be a divided version (/1, /2, /3, /4) of CLKI. CLKI is typically derived from the host CPU bus clock. The source clock options for BCLK may be selected as in the following table. Table 7-1: BCLK Clock Selection
Source Clock Options CLKI CLKI /2 CLKI /3 CLKI /4 BCLK Selection CNF[7:6] = 00 CNF[7:6] = 01 CNF[7:6] = 10 CNF[7:6] = 11
Note
For synchronous bus interfaces, it is recommended that BCLK be set the same as the CPU bus clock (not a divided version of CLKI) e.g. SH-3, SH-4.
Note
The CLKI / 3 and CLKI / 4 options may not work properly with bus interfaces with short back-to-back cycle timing.
7.1.2 MCLK
MCLK provides the internal clock required to access the embedded SRAM. The S1D13706 is designed with efficient power saving control for clocks (clocks are turned off when not used); reducing the frequency of MCLK does not necessarily save more power. Furthermore, reducing the MCLK frequency relative to the BCLK frequency increases the CPU cycle latency and so reduces screen update performance. For a balance of power saving and performance, the MCLK should be configured to have a high enough frequency setting to provide sufficient screen refresh as well as acceptable CPU cycle latency. The source clock options for MCLK may be selected as in the following table. Table 7-2: MCLK Clock Selection
Source Clock Options BCLK BCLK /2 BCLK /3 BCLK /4
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MCLK Selection REG[04h] bit 5,4 = 00 REG[04h] bit 5,4 = 01 REG[04h] bit 5,4 = 10 REG[04h] bit 5,4 = 11
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7.1.3 PCLK
PCLK is the internal clock used to control the LCD panel. PCLK should be chosen to match the optimum frame rate of the LCD panel. See Section 9, "Frame Rate Calculation" on page 130 for details on the relationship between PCLK and frame rate. Some flexibility is possible in the selection of PCLK. Firstly, LCD panels typically have a range of permissible frame rates. Secondly, it may be possible to choose a higher PCLK frequency and tailor the horizontal and vertical non-display periods to lower the frame-rate to its optimal value. The source clock options for PCLK may be selected as in the following table. Table 7-3: PCLK Clock Selection
Source Clock Options MCLK MCLK /2 MCLK /3 MCLK /4 MCLK /8 BCLK BCLK /2 BCLK /3 BCLK /4 BCLK /8 CLKI CLKI /2 CLKI /3 CLKI /4 CLKI /8 CLKI2 CLKI2 /2 CLKI2 /3 CLKI2 /4 CLKI2 /8 PCLK Selection REG[05h] = 00h REG[05h] = 10h REG[05h] = 20h REG[05h] = 30h REG[05h] = 40h REG[05h] = 01h REG[05h] = 11h REG[05h] = 21h REG[05h] = 31h REG[05h] = 41h REG[05h] = 02h REG[05h] = 12h REG[05h] = 22h REG[05h] = 32h REG[05h] = 42h REG[05h] = 03h REG[05h] = 13h REG[05h] = 23h REG[05h] = 33h REG[05h] = 43h
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There is a relationship between the frequency of MCLK and PCLK that must be maintained. Table 7-4: Relationship between MCLK and PCLK
SwivelView Orientation Color Depth (bpp) 16 8 SwivelView 0 and 180 4 2 1 SwivelView 90 and 270 16/8/4/2/1 MCLK to PCLK Relationship fMCLK fPCLK fMCLK fPCLK / 2 fMCLK fPCLK / 4 fMCLK fPCLK / 8 fMCLK fPCLK /16 fMCLK 1.25fPCLK
7.1.4 PWMCLK
PWMCLK is the internal clock used by the Pulse Width Modulator for output to the panel. The source clock options for PWMCLK may be selected as in the following table. Table 7-5: PWMCLK Clock Selection
Source Clock Options CLKI CLKI2 PWMCLK Selection REG[B1h] bit 0 = 0 REG[B1h] bit 0 = 1
For further information on controlling PWMCLK, see Section 8.3.9, "Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers" on page 126.
Note
The S1D13706 provides Pulse Width Modulation output on the pin PWMOUT. PWMOUT can be used to control LCD panels which support PWM control of the backlight inverter.
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7.2 Clock Selection
The following diagram provides a logical representation of the S1D13706 internal clocks.
CLKI /2 /3 /4
00 01 BCLK 10 11
CNF[7:6]1
REG[04h] bits 5,4
00 /2 /3 /4 01 MCLK 10 11
00 01 000 10 CLKI2 11 /2 /3 /4 /8 001 010 011 1xx PCLK
REG[05h] bits 1,0
0 1
REG[05h] bits 6-4 PWMCLK
REG[B1h] bit 0
Figure 7-1: Clock Selection
Note
1
CNF[7:6] must be set at RESET#.
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7.3 Clocks versus Functions
Table 7-6: "S1D13706 Internal Clock Requirements", lists the internal clocks required for the following S1D13706 functions. Table 7-6: S1D13706 Internal Clock Requirements
Function Register Read/Write Memory Read/Write Look-Up Table Register Read/Write Software Power Save LCD Output Bus Clock (BCLK) Required Required Required Required Required Memory Clock (MCLK) Not Required Required Required Not Required Required Pixel Clock (PCLK) Not Required Not Required Not Required Not Required Required PWM Clock (PWMCLK) Not Required1 Not Required1 Not Required1 Not Required1 Not Required1
Note
1
PWMCLK is an optional clock (see Section 7.1.4, "PWMCLK" on page 92).
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8 Registers
This section discusses how and where to access the S1D13706 registers. It also provides detailed information about the layout and usage of each register.
8.1 Register Mapping
The S1D13706 registers are memory-mapped. When the system decodes the input pins as CS# = 0 and M/R# = 0, the registers may be accessed. The register space is decoded by A[16:0].
8.2 Register Set
The S1D13706 register set is as follows. Table 8-1: S1D13706 Register Set
Register
REG[00h] Revision Code Register REG[02h] Configuration Readback Register
Pg Read-Only Configuration Registers
96 97
Register
REG[01h] Display Buffer Size Register
Pg
97
Clock Configuration Registers
REG[04h] Memory Clock Configuration Register 97 REG[05h] Pixel Clock Configuration Register 98
Look-Up Table Registers
REG[08h] Look-Up Table Blue Write Data Register REG[0Ah] Look-Up Table Red Write Data Register REG[0Ch] Look-Up Table Blue Read Data Register REG[0Eh] Look-Up Table Red Read Data Register 99 99 100 101 REG[09h] Look-Up Table Green Write Data Register REG[0Bh] Look-Up Table Write Address Register REG[0Dh] Look-Up Table Green Read Data Register REG[0Fh] Look-Up Table Read Address Register 99 100 100 101
Panel Configuration Registers
REG[10h] Panel Type Register REG[12h] Horizontal Total Register REG[16h] Horizontal Display Period Start Position Register 0 REG[18h] Vertical Total Register 0 REG[1Ch] Vertical Display Period Register 0 REG[1Eh] Vertical Display Period Start Position Register 0 REG[20h] FPLINE Pulse Width Register REG[23h] FPLINE Pulse Start Position Register 1 REG[26h] FPFRAME Pulse Start Position Register 0 REG[28h] D-TFD GCP Index Register 101 103 104 105 105 106 106 107 108 108 REG[11h] MOD Rate Register REG[14h] Horizontal Display Period Register REG[17h] Horizontal Display Period Start Position Register 1 REG[19h] Vertical Total Register 1 REG[1Dh] Vertical Display Period Register 1 REG[1Fh] Vertical Display Period Start Position Register 1 REG[22h] FPLINE Pulse Start Position Register 0 REG[24h] FPFRAME Pulse Width Register REG[27h] FPFRAME Pulse Start Position Register 1 REG[2Ch] D-TFD GCP Data Register 103 103 104 105 105 106 107 107 108 108
Display Mode Registers
REG[70h] Display Mode Register REG[74h] Main Window Display Start Address Register 0 REG[76h] Main Window Display Start Address Register 2 REG[79h] Main Window Line Address Offset Register 1 109 113 113 114 REG[71h] Special Effects Register REG[75h] Main Window Display Start Address Register 1 REG[78h] Main Window Line Address Offset Register 0 111 113 114
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Table 8-1: S1D13706 Register Set
Register
REG[7Ch] PIP+
+ +
Pg Picture-in-Picture Plus (PIP ) Registers
+
Register
REG[7Dh] PIP+ Window Display Start Address Register 1 REG[80h] PIP+ Window Line Address Offset Register 0 REG[84h] PIP Window X Start Position Register 0 REG[88h] PIP+ Window Y Start Position Register 0 REG[8Ch] PIP Window X End Position Register 0 REG[90h] PIP+ Window Y End Position Register 0
+ +
Pg
115 115 116 117 118 119
Window Display Start Address Register 0
115 115 115 116 117 118 119
REG[7Eh] PIP Window Display Start Address Register 2 REG[81h] PIP Window Line Address Offset Register 1 REG[85h] PIP+ Window X Start Position Register 1 REG[89h] PIP Window Y Start Position Register 1 REG[8Dh] PIP+ Window X End Position Register 1 REG[91h] PIP+ Window Y End Position Register 1
+
Miscellaneous Registers
REG[A0h] Power Save Configuration Register REG[A2h] Reserved REG[A4h] Scratch Pad Register 0 120 121 121 REG[A1h] Reserved REG[A3h] Reserved REG[A5h] Scratch Pad Register 1 120 121 121
General Purpose IO Pins Registers
REG[A8h] General Purpose IO Pins Configuration Register 0 122 REG[A9h] General Purpose IO Pins Configuration Register 1 122 REG[ACh] General Purpose IO Pins Status/Control Register 0 123 REG[ADh] General Purpose IO Pins Status/Control Register 1 125
PWM Clock and CV Pulse Configuration Registers
REG[B0h] PWM Clock / CV Pulse Control Register REG[B2h] CV Pulse Burst Length Register 126 129 REG[B1h] PWM Clock / CV Pulse Configuration Register REG[B3h] PWMOUT Duty Cycle Register 128 129
8.3 Register Descriptions
Unless specified otherwise, all register bits are set to 0 during power-on.
8.3.1 Read-Only Configuration Registers
Revision Code Register REG[00h]
Product Code Bits 5-0
7 6 5 4 3 2
Read Only
Revision Code Bits 1-0
1 0
Note
The S1D13706 returns a value of 28h. bits 7-2 bits 1-0 Product Code These are read-only bits that indicates the product code. The product code is 001010. Revision Code These are read-only bits that indicates the revision code. The revision code is 00.
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Display Buffer Size Register REG[01h]
Display Buffer Size Bits 7-0
7 6 5 4 3 2 1
Read Only
0
bits 7-0
Display Buffer Size Bits [7:0] This is a read-only register that indicates the size of the SRAM display buffer measured in 4K byte increments. The S1D13706 display buffer is 80K bytes and therefore this register returns a value of 20 (14h). Value of this register = display buffer size / 4K bytes = 80K bytes / 4K bytes = 20 (14h)
Configuration Readback Register REG[02h]
CNF7 Status
7
Read Only
CNF4 Status
4
CNF6 Status CNF5 Status
6 5
CNF3 Status
3
CNF2 Status
2
CNF1 Status
1
CNF0 Status
0
bits 7-0
CNF[7:0] Status These read-only status bits return the status of the configuration pins CNF[7:0]. CNF[7:0] are latched at the rising edge of RESET#.
8.3.2 Clock Configuration Registers
Memory Clock Configuration Register REG[04h]
n/a
7 6
Read/Write
n/a
3 2 1
MCLK Divide Select Bits 1-0
5 4
Reserved
0
bits 5-4
MCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Memory Clock (MCLK) from the Bus Clock (BCLK). Table 8-2: MCLK Divide Selection
MCLK Divide Select Bits 00 01 10 11 BCLK to MCLK Frequency Ratio 1:1 2:1 3:1 4:1
bit 0
Reserved. This bit must remain at 0.
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Pixel Clock Configuration Register REG[05h]
n/a
7 6
Read/Write
n/a
4 3 2
PCLK Divide Select Bits 2-0
5
PCLK Source Select Bits 1-0
1 0
bits 6-4
PCLK Divide Select Bits [1:0] These bits determine the divide used to generate the Pixel Clock (PCLK) from the Pixel Clock Source. Table 8-3: PCLK Divide Selection
PCLK Divide Select Bits 000 001 010 011 1XX PCLK Source to PCLK Frequency Ratio 1:1 2:1 3:1 4:1 8:1
bits 1-0
PCLK Source Select Bits [1:0] These bits determine the source of the Pixel Clock (PCLK). Table 8-4: PCLK Source Selection
PCLK Source Select Bits 00 01 10 11 PCLK Source MCLK BCLK CLKI CLKI2
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8.3.3 Look-Up Table Registers
Note
The S1D13706 has three 256-position, 6-bit wide LUTs, one for each of red, green, and blue (see Section 11, "Look-Up Table Architecture" on page 132).
Look-Up Table Blue Write Data Register REG[08h]
LUT Blue Write Data Bits 5-0
7 6 5 4 3 2 1
Write Only
n/a
0
bits 7-2
LUT Blue Write Data Bits [5:0] This register contains the data to be written to the blue component of the Look-Up Table. The data is stored in this register until a write to the LUT Write Address register (REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written to.
Look-Up Table Green Write Data Register REG[09h]
LUT Green Write Data Bits 5-0
7 6 5 4 3 2 1
Write Only
n/a
0
bits 7-2
LUT Green Write Data Bits [5:0] This register contains the data to be written to the green component of the Look-Up Table. The data is stored in this register until a write to the LUT Write Address register (REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written to.
Look-Up Table Red Write Data Register REG[0Ah]
LUT Red Write Data Bits 5-0
7 6 5 4 3 2 1
Write Only
n/a
0
bits 7-2
LUT Red Write Data Bits [5:0] This register contains the data to be written to the red component of the Look-Up Table. The data is stored in this register until a write to the LUT Write Address register (REG[0Bh]) moves the data into the Look-Up Table.
Note
The LUT entry is updated only when the LUT Write Address Register (REG[0Bh]) is written to.
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Look-Up Table Write Address Register REG[0Bh]
LUT Write Address Bits 7-0
7 6 5 4 3 2 1
Write Only
0
bits 7-0
LUT Write Address Bits [7:0] This register forms a pointer into the Look-Up Table (LUT) which is used to write LUT blue, green, and red data stored in REG[08h], REG[09h], and REG[0Ah]. The data is updated to the LUT only with the completion of a write to this register. This is a writeonly register and returns 00h if read.
Note
When a value is written to the LUT Write Address register, the same value is automatically written to the LUT Read Address register (REG[0Fh].
Look-Up Table Blue Read Data Register REG[0Ch]
LUT Blue Read Data Bits 5-0
7 6 5 4 3 2 1
Read Only
n/a
0
bits 7-2
LUT Blue Read Data Bits [5:0] This register contains the data from the blue component of the Look-Up Table. The LUT position is controlled by the LUT Read Address Register (REG[0Fh]). This is a read-only register.
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written to.
Look-Up Table Green Read Data Register REG[0Dh]
LUT Green Read Data Bits 5-0
7 6 5 4 3 2 1
Read Only
n/a
0
bits 7-2
LUT Green Read Data Bits [5:0] This register contains the data from the green component of the Look-Up Table. The LUT position is controlled by the LUT Read Address Register (REG[0Fh]). This is a read-only register.
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written to.
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Look-Up Table Red Read Data Register REG[0Eh]
LUT Red Read Data Bits 5-0
7 6 5 4 3 2 1
Read Only
n/a
0
bits 7-2
LUT Red Read Data Bits [5:0] This register contains the data from the red component of the Look-Up Table. The LUT position is controlled by the LUT Read Address Register (REG[0Fh]). This is a read-only register.
Note
This register is updated only when the LUT Read Address Register (REG[0Fh]) is written to.
Look-Up Table Read Address Register REG[0Fh]
LUT Read Address Bits 7-0
7 6 5 4 3 2 1
Write Only
0
bits 7-0
LUT Read Address Bits [7:0] This register forms a pointer into the Look-Up Table (LUT) which is used to read LUT blue, green, and red data. Blue data is read from REG[0Ch], green data from REG[0Dh], and red data from REG[0Eh]. This is a write-only register and returns 00h if read.
Note
If a write to the LUT Write Address register (REG[0Bh]) is made, the LUT Read Address register is automatically updated with the same value.
8.3.4 Panel Configuration Registers
Panel Type Register REG[10h]
Panel Data Format Select
7
Read/Write
Panel Data Width Bits 1-0
5 4
Color/Mono. Panel Select
6
Active Panel Resolution Select
3
n/a
2
Panel Type Bits 1-0
1 0
bit 7
Panel Data Format Select When this bit = 0, 8-bit single color passive LCD panel data format 1 is selected. For AC timing see Section 6.4.5, "Single Color 8-Bit Panel Timing (Format 1)" on page 66. When this bit = 1, 8-bit single color passive LCD panel data format 2 is selected. For AC timing see Section 6.4.6, "Single Color 8-Bit Panel Timing (Format 2)" on page 68. Color/Mono Panel Select When this bit = 0, a monochrome LCD panel is selected. When this bit = 1, a color LCD panel is selected.
bit 6
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bits 5-4
Panel Data Width Bits [1:0] These bits select the data width size of the LCD panel. Table 8-5: Panel Data Width Selection
Panel Data Width Bits [1:0] 00 01 10 11 Passive Panel Data Width Size 4-bit 8-bit 16-bit Reserved Active Panel Data Width Size 9-bit 12-bit 18-bit Reserved
bit 3
Active Panel Resolution Select This bit selects one of two panel resolutions when an HR-TFT or D-TFD panel is selected. This bit has no effect for other panel types. Table 8-6: Active Panel Resolution Selection
Active Panel Resolution Select Bit 0 1 HR-TFT Resolution 160x160 320x240 D-TFD Resolution 160x240 320x240
Note
This bit sets some internal non-configurable timing values for the selected panel. However, all panel configuration registers (REG[12h] - REG[27h]) still require programming with the appropriate values for the selected panel. For panel AC timing, see Section 6.4, "Display Interface" on page 56. bits 1-0 Panel Type Bits[1:0] These bits select the panel type. Table 8-7: LCD Panel Type Selection
REG[10h] Bits[1:0] 00 01 10 11 Panel Type STN TFT HR-TFT D-TFD
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MOD Rate Register REG[11h]
n/a
7 6 5 4
Read/Write
MOD Rate Bits 5-0
3 2 1 0
bits 5-0
MOD Rate Bits [5:0] These bits are for passive LCD panels only. When these bits are all 0, the MOD output signal (DRDY) toggles every FPFRAME. For a non-zero value n, the MOD output signal (DRDY) toggles every n FPLINE.
Horizontal Total Register REG[12h]
n/a
7 6 5 4
Read/Write
Horizontal Total Bits 6-0
3 2 1 0
bits 6-0
Horizontal Total Bits [6:0] These bits specify the LCD panel Horizontal Total period, in 8 pixel resolution. The Horizontal Total is the sum of the Horizontal Display period and the Horizontal Non-Display period. Since the maximum Horizontal Total is 1024 pixels, the maximum panel resolution supported is 800x600. Horizontal Total in number of pixels = ((REG[12h] bits 6:0) + 1) x 8
Note
This register must be programmed such that the following formulas are valid. HDPS + HDP < HT 2 For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
1
Horizontal Display Period Register REG[14h]
n/a
7 6 5
Read/Write
Horizontal Display Period Bits 6-0
4 3 2 1 0
bits 6-0
Horizontal Display Period Bits [6:0] These bits specify the LCD panel Horizontal Display Period (HDP), in 8 pixel resolution. The Horizontal Display Period should be less than the Horizontal Total to allow for a sufficient Horizontal Non-Display Period. Horizontal Display Period in number of pixels = ((REG[14h] bits 6:0) + 1) x 8
Note
For passive panels, HDP must be a minimum of 32 pixels and can be increased by multiples of 16. For TFT panels, HDP must be a minimum of 16 pixels and can be increased by multiples of 8. For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
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Horizontal Display Period Start Position Register 0 REG[16h]
Horizontal Display Period Start Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Horizontal Display Period Start Position Register 1 REG[17h]
n/a
7 6 5 4 3 2
Read/Write
Horizontal Display Period Start Position Bits 9-8
1 0
bits 9-0
Horizontal Display Period Start Position Bits [9:0] These bits specify a value used in the calculation of the Horizontal Display Period Start Position (in 1 pixel resolution) for TFT, HR-TFT and D-TFD panels. For passive LCD panels these bits must be set to 00h which will result in HDPS = 22. HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 22 For TFT/HR-TFT/D-TFD panels, HDPS is calculated using the following formula. HDPS = (REG[17h] bits 1-0, REG[16h] bits 7-0) + 5 For further information on calculating the HDPS, see the specific panel AC Timing in Section 6.4, "Display Interface" on page 56.
Note
This register must be programmed such that the following formula is valid. HDPS + HDP < HT
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Vertical Total Register 0 REG[18h]
Vertical Total Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Vertical Total Register 1 REG[19h]
n/a
7 6 5 4 3 2
Read/Write
Vertical Total Bits 9-8
1 0
bits 9-0
Vertical Total Bits [9:0] These bits specify the LCD panel Vertical Total period, in 1 line resolution. The Vertical Total is the sum of the Vertical Display Period and the Vertical Non-Display Period. The maximum Vertical Total is 1024 lines. Vertical Total in number of lines = (REG[18h] bits 7:0, REG[19h] bits 1:0) + 1
Note
This register must be programmed such that the following formula is valid. VDPS + VDP < VT 2 For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
1
Vertical Display Period Register 0 REG[1Ch]
Vertical Display Period Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Vertical Display Period Register 1 REG[1Dh]
n/a
7 6 5 4 3 2
Read/Write
Vertical Display Period Bits 9-8
1 0
bits 9-0
Vertical Display Period Bits [9:0] These bits specify the LCD panel Vertical Display period, in 1 line resolution. The Vertical Display period should be less than the Vertical Total to allow for a sufficient Vertical Non-Display period. Vertical Display Period in number of lines = (REG[1Ch] bits 7:0, REG[1Dh] bits 1:0) + 1
Note
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
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Vertical Display Period Start Position Register 0 REG[1Eh]
Vertical Display Period Start Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Vertical Display Period Start Position Register 1 REG[1Fh]
n/a
7 6 5 4 3 2
Read/Write
Vertical Display Period Start Position Bits 9-8
1 0
bits 9-0
Vertical Display Period Start Position Bits [9:0] These bits specify the Vertical Display Period Start Position for panels in 1 line resolution. For passive LCD panels these bits must be set to 00h. For TFT panels, VDPS is calculated using the following formula. VDPS = (REG[1Fh] bits 1-0, REG[1Eh] bits 7-0)
Note
This register must be programmed such that the following formula is valid. VDPS + VDP < VT 2 For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
1
FPLINE Pulse Width Register REG[20h]
FPLINE Pulse Polarity
7 6 5 4
Read/Write
FPLINE Pulse Width Bits 6-0
3 2 1 0
bit 7
FPLINE Pulse Polarity This bit selects the polarity of the horizontal sync signal. For passive panels, this bit must be set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel (typically FPLINE or LP). When this bit = 0, the horizontal sync signal is active low. When this bit = 1, the horizontal sync signal is active high. FPLINE Pulse Width Bits [6:0] These bits specify the width of the panel horizontal sync signal, in 1 pixel resolution. The horizontal sync signal is typically FPLINE or LP, depending on the panel type. FPLINE Pulse Width in number of pixels = (REG[20h] bits 6:0) + 1
Note
bits 6-0
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
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FPLINE Pulse Start Position Register 0 REG[22h]
FPLINE Pulse Start Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
FPLINE Pulse Start Position Register 1 REG[23h]
n/a
7 6 5 4 3 2
Read/Write
FPLINE Pulse Start Position Bits 9-8
1 0
bits 9-0
FPLINE Pulse Start Position Bits [9:0] These bits specify the start position of the horizontal sync signal, in 1 pixel resolution. FPLINE Pulse Start Position in pixels = (REG[23h] bits 1-0, REG[22h] bits 7-0) + 1
Note
For passive panels, these bits must be programmed such that the following formula is valid. HPW + HPS < HT
Note
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
FPFRAME Pulse Width Register REG[24h]
FPFRAME Pulse Polarity
7 6 5
Read/Write
n/a
4 3
FPFRAME Pulse Width Bits 2-0
2 1 0
bit 7
FPFRAME Pulse Polarity This bit selects the polarity of the vertical sync signal. For passive panels, this bit must be set to 1. For TFT panels, this bit is set according to the horizontal sync signal of the panel (typically FPFRAME, SPS or DY). When this bit = 0, the vertical sync signal is active low. When this bit = 1, the vertical sync signal is active high. FPFRAME Pulse Width Bits [2:0] These bits specify the width of the panel vertical sync signal, in 1 line resolution. The vertical sync signal is typically FPFRAME, SPS or DY, depending on the panel type. FPFRAME Pulse Width in number of lines = (REG[24h] bits 2:0) + 1
Note
bits 2-0
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
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FPFRAME Pulse Start Position Register 0 REG[26h]
FPFRAME Pulse Start Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
FPFRAME Pulse Start Position Register 1 REG[27h]
n/a
7 6 5 4 3 2
Read/Write
FPFRAME Pulse Start Position Bits 9-8
1 0
bits 9-0
FPFRAME Pulse Start Position Bits [9:0] These bits specify the start position of the vertical sync signal, in 1 line resolution. For passive panels, these bits must be set to 00h. For TFT/HR-TFT/D-TFD panels, VDPS is calculated using the following formula: VPS = (REG[27h] bits 1-0, REG[26h] bits 7-0)
Note
For panel AC timing and timing parameter definitions, see Section 6.4, "Display Interface" on page 56.
D-TFD GCP Index Register REG[28h]
n/a
7 6 5 4 3
Read/Write
D-TFD GCP Index Bits 4-0
2 1 0
bits 4-0
D-TFD GCP Index Bits [4:0] For D-TFD panels only. These bits form the index that points to 32 8-bit GCP data registers.
D-TFD GCP Data Register REG[2Ch]
D-TFD GCP Data Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
bits 7-0
D-TFD GCP Data Bits [7:0] For D-TFD panel only. This register stores the data to be written to the GCP data bits and is controlled by the D-TFD GCP Index register (REG[28h]). For further information on the use of this register, see Connecting to the Epson D-TFD Panels, document number X31B-G-012-xx.
Note
The Panel Type bits (REG[10h] bits 1:0) must be set to 11 (D-TFD) for the GCP Data bits to have any hardware effect.
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8.3.5 Display Mode Registers
Display Mode Register REG[70h]
Display Blank
7
Read/Write
Hardware Video Invert Enable
5
Dithering Disable
6
Software Video Invert
4
n/a
3 2
Bit-per-pixel Select Bits 2-0
1 0
bit 7
Display Blank When this bit = 0, the LCD display pipeline is enabled. When this bit = 1, the LCD display pipeline is disabled and all LCD data outputs are forced to zero (i.e., the screen is blanked). Dithering Disable Dithering allows 64 intensity levels for each color component (RGB). In monochrome modes where only the Green color component of the Look-Up-Table is used, 64 shades of gray are available for each position used in the LUT. In color modes, 64 shades of color are available for each color component resulting in 256K possible color combinations. When this bit = 0, dithering is enabled for passive LCD panels. When this bit = 1, dithering is disabled for passive LCD panels.
Note
bit 6
This bit does not refer to the number of simultaneously displayed colors but rather the maximum available colors (refer to Table 8-9: "LCD Bit-per-pixel Selection," on page 111 for the maximum number of simultaneously displayed colors).
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bit 5
Hardware Video Invert Enable This bit allows the Video Invert feature to be controlled using the General Purpose IO pin GPIO0. This option is not available if configured for a HR-TFT or D-TFD as GPIO0 is used as an LCD control signal by both panels. When this bit = 0, GPIO0 has no effect on the video data. When this bit = 1, video data may be inverted via GPIO0.
Note
The S1D13706 requires some configuration before the hardware video invert feature can be enabled. * CNF3 must be set to 1 at RESET# * GPIO Pin Input Enable (REG[A9h] bit 7) must be set to 1 * GPIO0 Pin IO Configuration (REG[A8h] bit 0) must be set to 0 If Hardware Video Invert is not available (i.e. HR-TFT panel is used), the video invert function can be controlled by software using REG[70h] bit 4. The following table summarizes the video invert options available. Table 8-8: Inverse Video Mode Select Options
Hardware Video Invert Enable 0 0 1 1 Software Video Invert 0 1 X X GPIO0 X X 0 1 Video Data Normal Inverse Normal Inverse
Note
Video data is inverted after the Look-Up Table. bit 4 Software Video Invert When this bit = 0, video data is normal. When this bit = 1, video data is inverted. See Table 8-8: "Inverse Video Mode Select Options".
Note
Video data is inverted after the Look-Up Table
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bits 2-0
Bit-per-pixel Select Bits [2:0] These bits select the color depth (bit-per-pixel) for the displayed data for both the main window and the PIP+ window (if active).
Note
1, 2, 4 and 8 bpp color depths use the 18-bit LUT, allowing a maximum number of 256K available colors on TFT panels. 16 bpp mode bypasses the LUT, allowing a maximum of only 64K available colors. Table 8-9: LCD Bit-per-pixel Selection
Bit-per-pixel Color Depth (bpp) Select Bits [2:0] 000 001 010 011 100 101, 110, 111 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp Maximum Number of Available Colors/Shades Passive Panel (Dithering On) 64K/64 64K/64 64K/64 64K/64 64K/64 Reserved TFT Panel 256K/64 256K/64 256K/64 256K/64 64K/64 Max. No. Of Simultaneously Displayed Colors/Shades 2/2 4/4 16/16 256/64 64K/64
Special Effects Register REG[71h]
Display Data Word Swap
7
Read/Write
n/a
5
Display Data Byte Swap
6
PIP Window Enable
4 3
+
n/a
2
SwivelView Mode Select Bits 1-0
1 0
bit 7
Display Data Word Swap The display pipe fetches 32-bits of data from the display buffer. This bit enables the lower 16-bit word and the upper 16-bit word to be swapped before sending them to the LCD display. If the Display Data Byte Swap bit is also enabled, then the byte order of the fetched 32-bit data is reversed.
Note
For further information on byte swapping for Big Endian mode, see Section 14, "BigEndian Bus Interface" on page 146.
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bit 6
Display Data Byte Swap The display pipe fetches 32-bits of data from the display buffer. This bit enables byte 0 and byte 1 to be swapped, and byte 2 and byte 3 to be swapped, before sending them to the LCD display. If the Display Data Word Swap bit is also enabled, then the byte order of the fetched 32-bit data is reversed.
byte 0 32-bit display data from display buffer byte 1 Data byte 2 byte 3 Byte Swap Word Swap Serialization To LUT
Figure 8-1: Display Data Byte/Word Swap
Note
For further information on byte swapping for Big Endian mode, see Section 14, "BigEndian Bus Interface" on page 146. bit 4 Picture-in-Picture Plus (PIP+) Window Enable This bit enables the PIP+ window within the main window used for the Picture-in-Picture Plus feature. The location of the PIP+ window within the landscape window is determined by the PIP+ Window X Position registers (REG[84h], REG[85h], REG[8Ch], REG[8Dh]) and PIP+ Window Y Position registers (REG[88h], REG[89h], REG[90h], REG[91h]). The PIP+ window has its own Display Start Address register (REG[7Ch], REG[7Dh], REG[7Eh]) and Memory Address Offset register (REG[80h], REG[81h]). The PIP+ window shares the same color depth and SwivelViewTM orientation as the main window. SwivelView Mode Select Bits [1:0] These bits select different SwivelViewTM orientations: Table 8-10: SwivelViewTM Mode Select Options
SwivelView Mode Select Bits 00 01 10 11 SwivelView Orientation 0 (Normal) 90 180 270
bit 1-0
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Main Window Display Start Address Register 0 REG[74h]
Main window Display Start Address Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Main Window Display Start Address Register 1 REG[75h]
Main window Display Start Address Bits 15-8
7 6 5 4 3 2 1
Read/Write
0
Main Window Display Start Address Register 2 REG[76h]
n/a
7 6 5 4 3 2 1
Read/Write
Main window Display Start Address Bit 16
0
bits 16-0
Main Window Display Start Address Bits [16:0] This register specifies the starting address, in DWORDS, for the LCD image in the display buffer for the main window. Note that this is a double-word (32-bit) address. An entry of 00000h into these registers represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on. Calculate the Display Start Address as follows: Main Window Display Start Address bits 16:0 = image address / 4 (valid only for SwivelView 0)
Note
For information on setting this register for other SwivelView orientations, see Section 12, "SwivelViewTM" on page 138.
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Main Window Line Address Offset Register 0 REG[78h]
Main window Line Address Offset Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Main Window Line Address Offset Register 1 REG[79h]
n/a
7 6 5 4 3 2
Read/Write
Main window Line Address Offset Bits 9-8
1 0
bits 9-0
Main Window Line Address Offset Bits [9:0] This register specifies the offset, in DWORDS, from the beginning of one display line to the beginning of the next display line in the main window. Note that this is a 32-bit address increment. Calculate the Line Address Offset as follows: Main Window Line Address Offset bits 9:0 = display width in pixels / (32 / bpp)
Note
A virtual display can be created by programming this register with a value greater than the formula requires. When a virtual display is created the image width is larger than the display width and the displayed image becomes a window into the larger virtual image.
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8.3.6 Picture-in-Picture Plus (PIP+) Registers
PIP+ Window Display Start Address Register 0 REG[7C]
PIP+ Window Display Start Address Bits 7-0
7 6 5 4 3 2 1 0
Read/Write
PIP+ Window Display Start Address Register 1 REG[7Dh]
PIP+ Window Display Start Address Bits 15-8
7 6 5 4 3 2 1
Read/Write
0
PIP+ Window Display Start Address Register 2 REG[7Eh]
n/a
7 6 5 4 3 2 1
Read/Write
PIP+ Window Display Start Address Bit 16
0
bits 16-0
PIP+ Window Display Start Address Bits [16:0] These bits form the 17-bit address for the starting double-word of the PIP+ window. Note that this is a double-word (32-bit) address. An entry of 00000h into these registers represents the first double-word of display memory, an entry of 00001h represents the second double-word of the display memory, and so on.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit 4).
PIP+ Window Line Address Offset Register 0 REG[80h]
PIP+ Window Line Address Offset Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
PIP+ Window Line Address Offset Register 1 REG[81h]
+
Read/Write
PIP Window Line Address Offset Bits 9-8
4 3 2 1 0
n/a
7 6 5
bits 9-0
PIP+ Window Line Address Offset Bits [9:0] These bits are the LCD display's 10-bit address offset from the starting double-word of line "n" to the starting double-word of line "n + 1" for the PIP+ window. Note that this is a 32-bit address increment.
Note
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit 4).
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PIP+ Window X Start Position Register 0 REG[84h]
PIP+ Window X Start Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
PIP+ Window X Start Position Register 1 REG[85h]
+
Read/Write
PIP Window X Start Position Bits 9-8
4 3 2 1 0
n/a
7 6 5
bits 9-0
PIP Window X Start Position Bits [9:0] These bits determine the X start position of the PIP+ window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the X start position may not be a horizontal position value (only true in 0 and 180 SwivelView). For further information on defining the value of the X Start Position register, see Section 13, "Picture-in-Picture Plus (PIP+)" on page 143. The register is also incremented differently based on the SwivelView orientation. For 0 and 180 SwivelView the X start position is incremented by x pixels where x is relative to the current color depth. Table 8-11: 32-bit Address Increments for Color Depth
Color Depth 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp Pixel Increment (x) 32 16 8 4 2
+
For 90 and 270 SwivelView the X start position is incremented in 1 line increments. Depending on the color depth, some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit 4). 2 The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written and at the next vertical non-display period.
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PIP+ Window Y Start Position Register 0 REG[88h]
PIP+ Window Y Start Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
PIP+ Window Y Start Position Register 1 REG[89h]
+
Read/Write
PIP Window Y Start Position Bits 9-8
4 3 2 1 0
n/a
7 6 5
bits 9-0
PIP Window Y Start Position Bits [9:0] These bits determine the Y start position of the PIP+ window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the Y start position may not be a vertical position value (only true in 0 and 180 SwivelView). For further information on defining the value of the Y Start Position register, see Section 13, "Picture-in-Picture Plus (PIP+)" on page 143. The register is also incremented differently based on the SwivelView orientation. For 0 and 180 SwivelView the Y start position is incremented in 1 line increments. For 90 and 270 SwivelView the Y start position is incremented by y pixels where y is relative to the current color depth. Table 8-12: 32-bit Address Increments for Color Depth
Color Depth 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp Pixel Increment (y) 32 16 8 4 2
+
Depending on the color depth, some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit 4). 2 The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written and at the next vertical non-display period.
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PIP+ Window X End Position Register 0 REG[8Ch]
PIP+ Window X End Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
PIP+ Window X End Position Register 1 REG[8Dh]
+
Read/Write
PIP Window X End Position Bits 9-8
4 3 2 1 0
n/a
7 6 5
bits 9-0
PIP Window X End Position Bits [9:0] These bits determine the X end position of the PIP+ window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the X end position may not be a horizontal position value (only true in 0 and 180 SwivelView). For further information on defining the value of the X End Position register, see Section 13, "Picture-in-Picture Plus (PIP+)" on page 143. The register is also incremented differently based on the SwivelView orientation. For 0 and 180 SwivelView the X end position is incremented by x pixels where x is relative to the current color depth. Table 8-13: 32-bit Address Increments for Color Depth
Color Depth 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp Pixel Increment (x) 32 16 8 4 2
+
For 90 and 270 SwivelView the X end position is incremented in 1 line increments. Depending on the color depth, some of the higher bits in this register are unused because the maximum horizontal display width is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit 4). 2 The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written and at the next vertical non-display period.
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PIP+ Window Y End Position Register 0 REG[90h]
PIP+ Window Y End Position Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
PIP+ Window Y End Position Register 1 REG[91h]
+
Read/Write
PIP Window Y End Position Bits 9-8
4 3 2 1 0
n/a
7 6 5
bits 9-0
PIP Window Y End Position Bits [9:0] These bits determine the Y end position of the PIP+ window in relation to the origin of the panel. Due to the S1D13706 SwivelView feature, the Y end position may not be a vertical position value (only true in 0 and 180 SwivelView). For further information on defining the value of the Y End Position register, see Section 13, "Picture-in-Picture Plus (PIP+)" on page 143. The register is also incremented differently based on the SwivelView orientation. For 0 and 180 SwivelView the Y end position is incremented in 1 line increments. For 90 and 270 SwivelView the Y end position is incremented by y pixels where y is relative to the current color depth. Table 8-14: 32-bit Address Increments for Color Depth
Color Depth 1 bpp 2 bpp 4 bpp 8 bpp 16 bpp Pixel Increment (y) 32 16 8 4 2
+
Depending on the color depth, some of the higher bits in this register are unused because the maximum vertical display height is 1024 pixels.
Note
1
These bits have no effect unless the PIP+ Window Enable bit is set to 1 (REG[71h] bit 4). 2 The effect of REG[84h] through REG[91h] takes place only after REG[91h] is written and at the next vertical non-display period.
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8.3.7 Miscellaneous Registers
Power Save Configuration Register REG[A0h]
Vertical NonDisplay Period Status (RO)
7 6
Read/Write
Memory Controller Power Save Status (RO)
4 3 2
n/a
5
n/a
1
Power Save Mode Enable
0
bit 7
Vertical Non-Display Period Status This is a read-only status bit. When this bit = 0, the LCD panel output is in a Vertical Display Period. When this bit = 1, the LCD panel output is in a Vertical Non-Display Period. Memory Controller Power Save Status This read-only status bit indicates the power save state of the memory controller. When this bit = 0, the memory controller is powered up. When this bit = 1, the memory controller is powered down and the MCLK source can be turned off.
Note
bit 3
Memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes. bit 0 Power Save Mode Enable When this bit = 1, the software initiated power save mode is enabled. When this bit = 0, the software initiated power save mode is disabled. At reset, this bit is set to 1. For a summary of Power Save Mode, see Section 15, "Power Save Mode" on page 149.
Note
Memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes.
Reserved REG[A1h]
n/a
7 6 5 4 3 2 1
Read/Write
Reserved
0
bit 0
Reserved. This bit must remain at 0.
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Reserved REG[A2h]
Reserved
7 6 5 4
Read/Write
n/a
3 2 1
Reserved
0
bit 7 bit 0
Reserved. This bit must remain at 0. Reserved. This bit must remain at 0.
Reserved REG[A3h]
Reserved
7 6 5 4
Read/Write
n/a
3 2 1 0
bit 7
Reserved. This bit must remain at 0.
Scratch Pad Register 0 REG[A4h]
Scratch Pad Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
Scratch Pad Register 1 REG[A5h]
Scratch Pad Bits 15-8
7 6 5 4 3 2 1
Read/Write
0
bits 15-0
Scratch Pad Bits [15:0] This register contains general purpose read/write bits. These bits have no effect on hardware.
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8.3.8 General IO Pins Registers
General Purpose IO Pins Configuration Register 0 REG[A8h]
n/a
7
Read/Write
GPIO6 Pin IO GPIO5 Pin IO GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIO0 Pin IO Configuration Configuration Configuration Configuration Configuration Configuration Configuration
6 5 4 3 2 1 0
Note
If CNF3 = 0 at RESET#, then all GPIO pins are configured as outputs only and this register has no effect. This case allows the GPIO pins to be used by the HR-TFT/D-TFD panel interfaces. For a summary of GPIO usage for HR-TFT/D-TFD, see Table 4-9: "LCD Interface Pin Mapping," on page 30. 2 The input functions of the GPIO pins are not enabled until REG[A9h] bit 7 is set to 1. bit 6 GPIO6 Pin IO Configuration When this bit = 0 (default), GPIO6 is configured as an input pin. When this bit = 1, GPIO6 is configured as an output pin. GPIO5 Pin IO Configuration When this bit = 0 (default), GPIO5 is configured as an input pin. When this bit = 1, GPIO5 is configured as an output pin. GPIO4 Pin IO Configuration When this bit = 0 (default), GPIO4 is configured as an input pin. When this bit = 1, GPIO4 is configured as an output pin. GPIO3 Pin IO Configuration When this bit = 0 (default), GPIO3 is configured as an input pin. When this bit = 1, GPIO3 is configured as an output pin. GPIO2 Pin IO Configuration When this bit = 0 (default), GPIO2 is configured as an input pin. When this bit = 1, GPIO2 is configured as an output pin. GPIO1 Pin IO Configuration When this bit = 0 (default), GPIO1 is configured as an input pin. When this bit = 1, GPIO1 is configured as an output pin. GPIO0 Pin IO Configuration When this bit = 0 (default), GPIO0 is configured as an input pin. When this bit = 1, GPIO0 is configured as an output pin.
1
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
General Purpose IO Pins Configuration Register 1 REG[A9h]
GPIO Pin Input Enable
7 6 5 4
Read/Write
n/a
3 2 1 0
bit 7
GPIO Pin Input Enable This bit is used to enable the input function of the GPIO pins. It must be changed to a 1 after power-on reset to enable the input function of the GPIO pins (default is 0).
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General Purpose IO Pins Status/Control Register 0 REG[ACh]
n/a
7
Read/Write
GPIO2 Pin IO Status
2
GPIO6 Pin IO Status
6
GPIO5 Pin IO Status
5
GPIO4 Pin IO GPIO3 Pin IO Status Status
4 3
GPIO1 Pin IO GPIO0 Pin IO Status Status
1 0
Note
For information on GPIO pin mapping when HR-TFT/D-TFD panels are selected, see Table 4-9: "LCD Interface Pin Mapping," on page 30. bit 6 GPIO6 Pin IO Status When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO6 is configured as an output, writing a 1 to this bit drives GPIO6 high and writing a 0 to this bit drives GPIO6 low. When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO6 is configured as an input, a read from this bit returns the status of GPIO6. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO6 outputs the YSCLD signal automatically and writing to this bit has no effect. bit 5 GPIO5 Pin IO Status When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO5 is configured as an output, writing a 1 to this bit drives GPIO5 high and writing a 0 to this bit drives GPIO5 low. When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO5 is configured as an input, a read from this bit returns the status of GPIO5. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) and a 1 is written to this bit, the D-TFD signal DD_P1 signal is enabled. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11) and a 0 is written to this bit, the D-TFD signal DD_P1 signal is forced low. bit 4 GPIO4 Pin IO Status When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO4 is configured as an output, writing a 1 to this bit drives GPIO4 high and writing a 0 to this bit drives GPIO4 low. When a D-TFD panel is not selected (REG[10h] bits 1:0) and GPIO4 is configured as an input, a read from this bit returns the status of GPIO4. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO4 outputs the RES signal automatically and writing to this bit has no effect.
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bit 3
GPIO3 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is configured as an output, writing a 1 to this bit drives GPIO3 high and writing a 0 to this bit drives GPIO3 low. When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO3 is configured as an input, a read from this bit returns the status of GPIO3. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO3 outputs the FRS signal automatically and writing to this bit has no effect. When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO3 outputs the SPL signal automatically and writing to this bit has no effect.
bit 2
GPIO2 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO2 is configured as an output, writing a 1 to this bit drives GPIO2 high and writing a 0 to this bit drives GPIO2 low. When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO2 is configured as an input, a read from this bit returns the status of GPIO2. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO2 outputs the FR signal automatically and writing to this bit has no effect. When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO2 outputs the REV signal automatically and writing to this bit has no effect.
bit 1
GPIO1 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO1 is configured as an output, writing a 1 to this bit drives GPIO1 high and writing a 0 to this bit drives GPIO1 low. When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO1 is configured as an input, a read from this bit returns the status of GPIO1. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO1 outputs the YSCL signal automatically and writing to this bit has no effect. When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO1 outputs the CLS signal automatically and writing to this bit has no effect.
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bit 0
GPIO0 Pin IO Status When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is configured as an output, writing a 1 to this bit drives GPIO0 high and writing a 0 to this bit drives GPIO0 low. When neither a D-TFD panel or a HR-TFT are selected (REG[10h] bits 1:0) and GPIO0 is configured as an input, a read from this bit returns the status of GPIO0. When a D-TFD panel is enabled (REG[10h] bits 1:0 = 11), GPIO0 outputs the XINH signal automatically and writing to this bit has no effect. When a HR-TFT panel is enabled (REG[10h] bits 1:0 = 10), GPIO0 outputs the PS signal automatically and writing to this bit has no effect.
General Purpose IO Pins Status/Control Register 1 REG[ADh]
GPO Control
7 6 5 4
Read/Write
n/a
3 2 1 0
bit 7
GPO Control This bit controls the General Purpose Output pin. Writing a 0 to this bit drives GPO to low. Writing a 1 to this bit drives GPO to high.
Note
Many implementations use the GPO pin to control the LCD bias power (see Section 6.3, "LCD Power Sequencing" on page 54).
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8.3.9 Pulse Width Modulation (PWM) Clock and Contrast Voltage (CV) Pulse Configuration Registers
PWM Clock Enable PWM Clock Divider Clock Source / 2
m
Divided Clock
PWMCLK
PWM Duty Cycle Modulation Duty = n / 256
n = PWM Clock Duty Cycle
to PWMOUT frequency = Clock Source / (2m X 256)
m = PWM Clock Divide Select value
PWM Clock Force High CV Pulse Enable CV Pulse Divider Clock Source / 2 x
x = CV Pulse Divide Select value
Divided Clock
CV Pulse Burst Generation y-pulse burst
to CVOUT
frequency = Clock Source / (2x X 2)
y = Burst Length value
CV Pulse Force High
Figure 8-2: PWM Clock/CV Pulse Block Diagram
Note
For further information on PWMCLK, see Section 7.1.4, "PWMCLK" on page 92.
PWM Clock / CV Pulse Control Register REG[B0h]
PWM Clock Force High
7 6
Read/Write
PWM Clock Enable CV Pulse Force High
3
n/a
5
CV Pulse Burst Status (RO)
2
CV Pulse Burst Start
1
CV Pulse Enable
0
4
bit 7 and bit 4
PWM Clock Force High (bit 7) and PWM Clock Enable (bit 4) These bits control the PWMOUT pin and PWM Clock circuitry as follows. Table 8-15: PWM Clock Control
Bit 7 0 0 1 Bit 4 1 0 x Result PWM Clock circuitry enabled (controlled by REG[B1h] and REG[B3h]) PWMOUT forced low PWMOUT forced high
x = don't care
When PWMOUT is forced low or forced high it can be used as a general purpose output.
Note
The PWM Clock circuitry is disabled when Power Save Mode is enabled.
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bit 3 and bit 0
CV Pulse Force High (bit 3) and CV Pulse Enable (bit 0) These bits control the CVOUT pin and CV Pulse circuitry as follows. Table 8-16: CV Pulse Control
Bit 3 0 0 1 Bit 0 1 0 x Result CV Pulse circuitry enabled (controlled by REG[B1h] and REG[B2h]) CVOUT forced low CVOUT forced high
x = don't care
When CVOUT is forced low or forced high it can be used as a general purpose output.
Note
Bit 3 must be set to 0 and bit 0 must be set to 1 before initiating a new burst using the CV Pulse Burst Start bit. 2 The CV Pulse circuitry is disabled when Power Save Mode is enabled. bit 2 CV Pulse Burst Status This is a read-only bit. A "1" indicates a CV pulse burst is occurring. A "0" indicates no CV pulse burst is occurring. Software should wait for this bit to clear before starting another burst. CV Pulse Burst Start A 1 in this bit initiates a single CVOUT pulse burst. The number of clock pulses generated is programmable from 1 to 256. The frequency of the pulses is the divided CV Pulse source divided by 2, with 50/50 duty cycle. This bit should be cleared to 0 by software before initiating a new burst.
Note
1
bit 1
This bit has effect only if the CV Pulse Enable bit is 1. bit 0 CV Pulse Enable See description for bit 3.
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PWM Clock / CV Pulse Configuration Register REG[B1h]
PWM Clock Divide Select Bits 3-0
7 6 5 4
Read/Write
CV Pulse Divide Select Bits 2-0
3 2 1
PWMCLK Source Select
0
bits 7-4
PWM Clock Divide Select Bits [3:0] The value of these bits represents the power of 2 by which the selected PWM clock source is divided. Table 8-17: PWM Clock Divide Select Options
PWM Clock Divide Select Bits [3:0] 0h 1h 2h 3h ... Ch Dh-Fh PWM Clock Divide Amount 1 2 4 8 ... 4096 Reserved
Note
This divided clock is further divided by 256 before it is output at PWMOUT. bits 3-1 CV Pulse Divide Select Bits [2:0] The value of these bits represents the power of 2 by which the selected CV Pulse source is divided. Table 8-18: CV Pulse Divide Select Options
CV Pulse Divide Select Bits [2:0] 0h 1h 2h 3h ... 7h CV Pulse Divide Amount 1 2 4 8 ... 128
Note
This divided clock is further divided by 2 before it is output at the CVOUT. bit 0 PWMCLK Source Select When this bit = 0, the clock source for PWMCLK is CLKI. When this bit = 1, the clock source for PWMCLK is CLKI2.
Note
For further information on the PWMCLK source select, see Section 7.2, "Clock Selection" on page 93.
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CV Pulse Burst Length Register REG[B2h]
CV Pulse Burst Length Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
bits 7-0
CV Pulse Burst Length Bits [7:0] The value of this register determines the number of pulses generated in a single CV Pulse burst: Number of pulses in a burst = (ContentsOfThisRegister) + 1
PWMOUT Duty Cycle Register REG[B3h]
PWMOUT Duty Cycle Bits 7-0
7 6 5 4 3 2 1
Read/Write
0
bits 7-0
PWMOUT Duty Cycle Bits [7:0] This register determines the duty cycle of the PWMOUT output. Table 8-19: PWMOUT Duty Cycle Select Options
PWMOUT Duty Cycle [7:0] 00h 01h 02h ... FFh PWMOUT Duty Cycle Always Low High for 1 out of 256 clock periods High for 2 out of 256 clock periods ... High for 255 out of 256 clock periods
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9 Frame Rate Calculation
The following formula is used to calculate the display frame rate.
f PCLK FrameRate = ------------------------------( HT ) x ( VT )
Where: fPCLK HT = PClk frequency (Hz) = Horizontal Total = ((REG[12h] bits 6-0) + 1) x 8 Pixels = Vertical Total = ((REG[19h] bits 1-0, REG[18h] bits 7-0) + 1) Lines
VT
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10 Display Data Formats
The following diagrams show the display mode data formats for a little-endian system.
1 bpp: bit 7 Byte 0 Byte 1 Byte 2 Host Address Display Memory 2 bpp: bit 7 Byte 0 Byte 1 Byte 2 Host Address Display Memory 4 bpp: bit 7 Byte 0 Byte 1 Byte 2 Host Address Display Memory 8 bpp: bit 7 Byte 0 Byte 1 Byte 2 Host Address Display Memory 16 bpp: Byte 0 Byte 1 Byte 2 Byte 3 Host Address Panel Display A0 A1 A2 B0 B1 B2 C0 C1 C2 D0 D1 D2 E0 E1 E2 F0 F1 F2 G0 G1 G2 bit 0 H0 H1 H2 LUT Pn = RGB value from LUT Index (An, Bn, Cn, Dn, En, Fn, Gn, Hn) P0 P1 P2 P3 P4 P5 P6 P7 Panel Display A0 A2 A4 B0 B2 B4 C0 C2 C4 D0 D2 D4 A1 A3 A5 B1 B3 B5 C1 C3 C5 bit 0 D1 D3 D5 LUT Pn = RGB value from LUT Index (An, Bn, Cn, Dn) P0 P1 P2 P3 P4 P5 P6 P7 Panel Display A0 A4 A8 B0 B4 B8 A1 A5 A9 B1 B5 B9 A2 A6 B2 B6 A3 A7 bit 0 B3 B7 LUT Pn = RGB value from LUT Index (An, Bn) P0 P1 P2 P3 P4 P5 P6 P7 Panel Display A0 A8 A1 A9 A2 A3 A4 A5 A6 bit 0 A7 LUT Pn = RGB value from LUT Index (An) P0 P1 P2 P3 P4 P5 P6 P7
A10 A11 A12 A13 A14 A15
A16 A17 A18 A19 A20 A21 A22 A23
A10 B10 A11 B11
5-6-5 RGB bit 7 bit 0 2 G1 0B4 G0 G0 B03 B02 B01 B00 0 0 R04 R03 R02 R01 R00 G05 G04 G03 G1 G11 R14 R13
2
P0 P1 P2 P3 P4 P5 P6 P7 Bypasses LUT Pn = (Rn4-0, Gn 5-0, Bn4-0)
G1
0
B1
4
B1
3
R12 R11 R10
B1 B11 G15 G14
2
B1
0
G 13 Panel Display
Display Buffer
Figure 10-1: 4/8/16 Bit-Per-Pixel Display Data Memory Organization
Note
1. The Host-to-Display mapping shown here is for a little endian system. 2. For 16 bpp format, Rn, Gn, Bn represent the red, green, and blue color components.
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11 Look-Up Table Architecture
The following figures are intended to show the display data output path only.
Note
When Video Data Invert is enabled the video data is inverted after the Look-Up Table.
11.1 Monochrome Modes
The green Look-Up Table (LUT) is used for all monochrome modes. 1 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6 00 01
00 01
6-bit Gray Data
FC FD FE FF 1 bit-per-pixel data from Display Buffer = unused Look-Up Table entries
Figure 11-1: 1 Bit-per-pixel Monochrome Mode Data Output Path 2 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6 00 01 02 03
00 01 10 11
6-bit Gray Data
FC FD FE FF 2 bit-per-pixel data from Display Buffer = unused Look-Up Table entries
Figure 11-2: 2 Bit-per-pixel Monochrome Mode Data Output Path
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4 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
6-bit Gray Data
FC FD FE FF 4 bit-per-pixel data from Display Buffer = unused Look-Up Table entries
Figure 11-3: 4 Bit-per-pixel Monochrome Mode Data Output Path 8 Bit-per-pixel Monochrome Mode
Green Look-Up Table 256x6 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF
0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111
6-bit Gray Data
1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111
8 bit-per-pixel data from Display Buffer
Figure 11-4: 8 Bit-per-pixel Monochrome Mode Data Output Path
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16 Bit-Per-Pixel Monochrome Mode The LUT is bypassed and the green data is directly mapped for this color depth- See "Display Data Formats" on page 131..
11.2 Color Modes
1 Bit-Per-Pixel Color
Red Look-Up Table 256x6 00 01
0 1
6-bit Red Data
FC FD FE FF
Green Look-Up Table 256x6 00 01
0 1
6-bit Green Data
FC FD FE FF
Blue Look-Up Table 256x6 00 01
0 1
6-bit Blue Data
FC FD FE FF
1 bit-per-pixel data from Image Buffer
= unused Look-Up Table entries
Figure 11-5: 1 Bit-Per-Pixel Color Mode Data Output Path
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2 Bit-Per-Pixel Color
Red Look-Up Table 256x6 00 01 02 03
00 01 10 11
6-bit Red Data
FC FD FE FF Green Look-Up Table 256x6 00 01 02 03
00 01 10 11
6-bit Green Data
FC FD FE FF Blue Look-Up Table 256x6 00 01 02 03
00 01 10 11
6-bit Blue Data
FC FD FE FF 2 bit-per-pixel data from Image Buffer = unused Look-Up Table entries
Figure 11-6: 2 Bit-Per-Pixel Color Mode Data Output Path
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4 Bit-Per-Pixel Color
Red Look-Up Table 256x6 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
6-bit Red Data
FC FD FE FF Green Look-Up Table 256x6 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
6-bit Green Data
FC FD FE FF Blue Look-Up Table 256x6 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
6-bit Blue Data
FC FD FE FF 4 bit-per-pixel data from Image Buffer
= unused Look-Up Table entries
Figure 11-7: 4 Bit-Per-Pixel Color Mode Data Output Path
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8 Bit-per-pixel Color Mode
Red Look-Up Table 256x6 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF
0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111
6-bit Red Data
1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111
Green Look-Up Table 256x6 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF
0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111
6-bit Green Data
1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111
Blue Look-Up Table 256x6 00 01 02 03 04 05 06 07 F8 F9 FA FB FC FD FE FF
0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111
6-bit Blue Data
1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111
8 bit-per-pixel data from Display Buffer
Figure 11-8: 8 Bit-per-pixel Color Mode Data Output Path 16 Bit-Per-Pixel Color Mode The LUT is bypassed and the color data is directly mapped for this color depth- See "Display Data Formats" on page 131.
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12 SwivelViewTM
12.1 Concept
Most computer displays are refreshed in landscape orientation - from left to right and top to bottom. Computer images are stored in the same manner. SwivelViewTM is designed to rotate the displayed image on an LCD by 90, 180, or 270 in an counter-clockwise direction. The rotation is done in hardware and is transparent to the user for all display buffer reads and writes. By processing the rotation in hardware, SwivelViewTM offers a performance advantage over software rotation of the displayed image. The image is not actually rotated in the display buffer since there is no address translation during CPU read/write. The image is rotated during display refresh.
12.2 90 SwivelViewTM
90 SwivelViewTM requires the Memory Clock (MCLK) to be at least 1.25 times the frequency of the Pixel Clock (PCLK), i.e. MCLK 1.25PCLK. The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A-B-C-D. The display is refreshed by the S1D13706 in the following sense: B-D-A-C.
physical memory start address A B
display start address (panel origin) D A
SwivelView window
C 320
480 image refreshed by S1D13706
image seen by programmer = image in display buffer
Figure 12-1: Relationship Between The Screen Image and the Image Refreshed in 90 SwivelView.
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C
320
SwivelView window
480
D
B
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12.2.1 Register Programming
Enable 90 SwivelViewTM Mode
Set SwivelViewTM Mode Select bits (REG[71h] bits 1:0) to 01.
Display Start Address
The display refresh circuitry starts at pixel "B", therefore the Main Window Display Start Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel "B". To calculate the value of the address of pixel "B" use the following formula (assumes 8 bpp color depth). Main Window Display Start Address bits 16:0 = ((image address + (panel height x bpp / 8)) / 4) - 1 = ((0 + (320 pixels x 8 bpp / 8)) / 4) -1 = 79 (4Fh)
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the display width and programmed using the following formula. Main Window Line Address Offset bits 9:0 = display width in pixels / (32 / bpp) = 320 pixels / 32 / 8 bpp = 80 (50h)
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12.3 180 SwivelViewTM
The following figure shows how the programmer sees a 480x320 landscape image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A-B-C-D. The display is refreshed by the S1D13706 in the following sense: D-C-B-A.
physical memory start address A SwivelView window C 480 image seen by programmer = image in display buffer D B 320 display start address (panel origin)
480 image refreshed by S1D13706
Figure 12-2: Relationship Between The Screen Image and the Image Refreshed in 180 SwivelView.
12.3.1 Register Programming
Enable 180 SwivelViewTM Mode
Set SwivelViewTM Mode Select bits (REG[71h] bits 1:0) to 10.
Display Start Address
The display refresh circuitry starts at pixel "D", therefore the Main Window Display Start Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel "D". To calculate the value of the address of pixel "D" use the following formula (assumes 8 bpp color depth). Main Window Display Start Address bits 16:0 = ((image address + (offset x (panel height - 1) + panel width) x bpp / 8) / 4) - 1 = ((0 + (480 pixels x 319 pixels + 480 pixels) x 8 bpp / 8) / 4) - 1 = 38399 (95FFh)
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320 A
C SwivelView window
D B
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Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the display width and programmed using the following formula. Main Window Line Address Offset bits 9:0 = display width in pixels / (32 / bpp) = 480 pixels / 32 / 8 bpp = 120 (78h)
12.4 270 SwivelViewTM
270 SwivelViewTM requires the Memory Clock (MCLK) to be at least 1.25 times the frequency of the Pixel Clock (PCLK), i.e. MCLK 1.25PCLK. The following figure shows how the programmer sees a 320x480 portrait image and how the image is being displayed. The application image is written to the S1D13706 in the following sense: A-B-C-D. The display is refreshed by the S1D13706 in the following sense: C-A-D-B.
physical memory start address A B
A
C
display start address (panel origin) D C 320 image seen by programmer = image in display buffer D
480 image refreshed by S1D13706
Figure 12-3: Relationship Between The Screen Image and the Image Refreshed in 270 SwivelView.
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480
SwivelView window
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12.4.1 Register Programming
Enable 270 SwivelViewTM Mode
Set SwivelViewTM Mode Select bits (REG[71h] bits 1:0) to 11. The display refresh circuitry starts at pixel "C", therefore the Main Window Display Start Address registers (REG[74h], REG[75h], REG[76h]) must be programmed with the address of pixel "C". To calculate the value of the address of pixel "C" use the following formula (assumes 8 bpp color depth). Main Window Display Start Address bits 16:0 = (image address + ((panel width - 1) x offset x bpp / 8) / 4) = (0 + ((480 pixels - 1) x 320 pixels x 8 bpp / 8) / 4) = 38320 (95B0h)
Line Address Offset
The Main Window Line Address Offset registers (REG[78h], REG[79h]) is based on the display width and programmed using the following formula. Main Window Line Address Offset bits 9:0 = display width in pixels / (32 / bpp) = 320 pixels / 32 / 8 bpp = 80 (50h)
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13 Picture-in-Picture Plus (PIP + )
13.1 Concept
Picture-in-Picture Plus enables a secondary window (or PIP+ window) within the main display window. The PIP+ window may be positioned anywhere within the virtual display and is controlled through the PIP+ window control registers (REG[7Ch] through REG[91h]). The PIP+ window retains the same color depth and SwivelView orientation as the main window. The following diagram shows an example of a PIP+ window within a main window and the registers used to position it.
0 SwivelViewTM
panel's origin
PIP+ window y start position (REG[89h],REG[88h]) PIP+ window y end position (REG[91h],REG[90h]) main-window
PIP+ window
PIP+ window x start position (REG[85h],REG[84h])
PIP+ window x end position (REG[8Dh],REG[8Ch])
Figure 13-1: Picture-in-Picture Plus with SwivelView disabled
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13.2 With SwivelView Enabled
13.2.1 SwivelView 90 90 SwivelViewTM
PIP+ window x end position (REG[8Dh],REG[8Ch]) PIP+ window panel's origin PIP+ window x start position (REG[85h],REG[84h])
PIP+ window y start position (REG[89h],REG[88h])
main-window
PIP+ window y end position (REG[91h],REG[90h])
Figure 13-2: Picture-in-Picture Plus with SwivelView 90 enabled
13.2.2 SwivelView 180 180 SwivelViewTM
PIP+ window x end position (REG[8Dh],REG[8Ch])
PIP+ window x start position (REG[85h],REG[84h])
PIP+ window
main-window
PIP+ window y end position (REG[91h],REG[90h])
PIP+ window y start position (REG[89h],REG[88h])
panel's origin
Figure 13-3: Picture-in-Picture Plus with SwivelView 180 enabled
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13.2.3 SwivelView 270 270 SwivelViewTM
PIP+ window y end position (REG[91h],REG[90h])
main-window
PIP+ window y start position (REG[89h],REG[88h])
PIP+ window
PIP+ window x start position (REG[85h],REG[84h]) panel's origin
PIP+ window x end position (REG[8Dh],REG[8Ch])
Figure 13-4: Picture-in-Picture Plus with SwivelView 270 enabled
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14 Big-Endian Bus Interface
14.1 Byte Swapping Bus Data
The display buffer and register architecture of the S1D13706 is inherently little-endian. If a host bus interface is configured as big-endian (CNF4 = 1 at reset), bus accesses are automatically handled by byte swapping all read/write data to/from the internal display buffer and registers. Bus data byte swapping translates all byte accesses correctly to the S1D13706 register and display buffer locations. To maintain the correct translation for 16-bit word access, even address bytes must be mapped to the MSB of the 16-bit word, and odd address bytes to the LSB of the 16-bit word. For example: Byte write 11h to register address 1Eh Byte write 22h to register address 1Fh -> -> REG[1Eh] <= 11h REG[1Fh] <= 22h REG[1Eh] <= 11h REG[1Fh] <= 22h
Word write 1122h to register address 1Eh->
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14.1.1 16 Bpp Color Depth
For 16 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 1.
D[15:8] D[7:0] 15 0 System Memory Address 2 0 aa cc bb dd CPU Data Byte Swap 15 bb dd aa cc 0 0 2 Display Data Byte Swap
Display Buffer Address
MSB
LSB
aabb
ccdd
System Memory (Big-Endian)
Display Buffer (Little-Endian)
* MSB is assumed to be associated with even address. * LSB is assumed to be associated with odd address.
Figure 14-1: Byte-swapping for 16 Bpp For 16 bpp color depth, the MSB of the 16-bit pixel data is stored at the even system memory address location and the LSB of the 16-bit pixel data is stored at the odd system memory address location. Bus data byte swapping (automatic when the S1D13706 is configured for Big-Endian) causes the 16-bit pixel data to be stored byte-swapped in the S1D13706 display buffer. During display refresh this stored data must be byte-swapped again before it is sent to the display.
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14.1.2 1/2/4/8 Bpp Color Depth
For 1/2/4/8 bpp color depth, byte swapping must be performed on the bus data but not the display data. For 1/2/4/8 bpp color depth, the Display Data Byte Swap bit (REG[71h] bit 6) must be set to 0.
D[15:8] D[7:0] 15 0 System Memory Address 0 11 22 CPU Data Byte Swap 15 22 11 0 0
Display Buffer Address
11 22
System Memory (Big-Endian)
Display Buffer (Little-Endian)
* High byte lane (D[15:8]) data (e.g. 11) is associated with even address. * Low byte lane (D[7:0]) data (e.g. 22) is associated with odd address.
Figure 14-2: Byte-swapping for 1/2/4/8 Bpp
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15 Power Save Mode
A software initiated Power Save Mode is incorporated into the S1D13706 to accommodate the need for power reduction in the hand-held devices market. This mode is enabled via the Power Save Mode Enable bit (REG[A0h] bit 0). Software Power Save Mode saves power by powering down the panel and stopping display refresh accesses to the display buffer. Table 15-1: Power Save Mode Function Summary
Software Power Save IO Access Possible? Memory Writes Possible? Memory Reads Possible? Look-Up Table Registers Access Possible? Sequence Controller Running? Display Active? LCD I/F Outputs PWMCLK GPIO Pins configured for HR-TFT/D-TFD2 GPIO Pins configured as GPIOs Access Possible?2 Yes Yes1 No
1
Normal Yes Yes Yes Yes Yes Yes Active Active Active Yes
Yes No No Forced Low Stopped Forced Low Yes3
Note
When power save mode is enabled, the memory controller is powered down and the status of the memory controller is indicated by the Memory Controller Power Save Status bit (REG[A0h] bit 3). However, memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes. 2 GPIO Pins are configured using the configuration pin CNF3 which is latched on the rising edge of RESET#. For information on CNF3, see Table 4-7: "Summary of PowerOn/Reset Options," on page 28. 3 GPIOs can be accessed and if configured as outputs can be changed. After reset, the S1D13706 is always in Power Save Mode. Software must initialize the chip (i.e. programs all registers) and then clear the Power Save Mode Enable bit.
1
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16 Mechanical Data
100-pin TQFP15 surface mount package
16.0 0.4 14.0 0.1 75 76 51 50
14.0 0.1 Index 100 1 1.0 0.1
+ 0.1
26 25 0.5
0.18 - 0.05
1.3 max.
0.125 - 0.025 0~10
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0.1
0.5 0.2 1
All dimensions in mm
Figure 16-1: Mechanical Data 100pin TQFP15 (S1D13706F00A)
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+ 0.05
16.0 0.4
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17 References
The following documents contain additional information related to the S1D13706. Document numbers are listed in parenthesis after the document name. All documents can be found at the Epson Research and Development Website at www.erd.epson.com. * 13706CFG Configuration Utility Users Manual (X31B-B-001-xx) * 13706SHOW Demonstration Program Users Manual (X31B-B-002-xx) * 13706PLAY Diagnostic Utility Users Manual (X31B-B-003-xx) * 13706BMP Demonstration Program Users Manual (X31B-B-004-xx) * S1D13706 Product Brief (X31B-C-001-xx) * S1D13706 Windows CE Display Drivers (X31B-E-001-xx) * Interfacing to the Toshiba TMPR3905/3912 Microprocessor (X31B-G-002-xx) * S1D13706 Programming Notes And Examples (X31B-G-003-xx) * S5U13706B00C Rev. 1.0 Evaluation Board User Manual (X31B-G-004-xx) * Interfacing to the PC Card Bus (X31B-G-005-xx) * S1D13706 Power Consumption (X31B-G-006-xx) * Interfacing to the NEC VR4102/VR4111 Microprocessors (X31B-G-007-xx) * Interfacing to the NEC VR4181 Microprocessor (X31B-G-008-xx) * Interfacing to the Motorola MPC821 Microprocessor (X31B-G-009-xx) * Interfacing to the Motorola MCF5307 "Coldfire" Microprocessors (X31B-G-010-xx) * Connecting to the Sharp HR-TFT Panels (X31B-G-011-xx) * Connecting to the Epson D-TFD Panels (X31B-G-012-xx) * Interfacing to the Motorola MC68030 Microprocessor (X31B-G-013-xx) * Interfacing to the Motorola RedCap2 DSP with Integrated MCU (X31B-G-014-xx) * Interfacing to 8-Bit Processors (X31B-G-015-xx) * Interfacing to the Motorola MC68VZ328 Dragonball Microprocessor (X31B-G-016-xx) * Integrating the CFLGA 104-pin Chip Scale Package (X31B-G-018-xx) * Interfacing to the Intel StrongARM SA-1110 Microprocessor (X31B-G-019-xx) * S1D13706 Register Summary (X31B-R-001-xx)
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18 Sales and Technical Support
Japan Seiko Epson Corporation Electronic Devices Marketing Division 421-8, Hino, Hino-shi Tokyo 191-8501, Japan Tel: 042-587-5812 Fax: 042-587-5564 http://www.epson.co.jp/ North America Epson Electronics America, Inc. 150 River Oaks Parkway San Jose, CA 95134, USA Tel: (408) 922-0200 Fax: (408) 922-0238 http://www.eea.epson.com/ Taiwan Epson Taiwan Technology & Trading Ltd. 10F, No. 287 Nanking East Road Sec. 3, Taipei, Taiwan Tel: 02-2717-7360 Fax: 02-2712-9164 http://www.epson.com.tw/ Singapore Epson Singapore Pte., Ltd. No. 1 Temasek Avenue #36-00 Millenia Tower Singapore, 039192 Tel: 337-7911 Fax: 334-2716 http://www.epson.com.sg/
Hong Kong Epson Hong Kong Ltd. 20/F., Harbour Centre 25 Harbour Road Wanchai, Hong Kong Tel: 2585-4600 Fax: 2827-4346 http://www.epson.com.hk/
Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich, Germany Tel: 089-14005-0 Fax: 089-14005-110 http://www.epson-electronics.de/
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